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KARL users

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Contents of this page List of other pages
KARL Licensee Sites
Early textual KARL-II implementation package
KARL language versions
Software interfaced to KARL, ABLED and RTcode
  (the KARL intermediate form)
Other KARL related software or KARL Dialects
Studies including KARL
Major designs implemented in using KARL and ABLED
KARL-related Quotation Index

KARL-related Literature

The nomination procedure:
Nomination Calendar
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About the candidate:
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Technical Presentations
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Theses directed
Advisory Activities
Serving Conferences and Journals
Serving Professional Organizations

KARL users
History of KARL
filled out B-27 Form from Prof Baier
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KARL users
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KARL stands for: KAiserslautern Register transfer Language (before Sept 1977, when Hartenstein joined Univ. of Kaiserslautern, KARL stood for: KArlsruhe Register transfer Language).

ABL stands for: A Block diagram Language (KARL sister language),

RTcode for Register Transfer code (KARL / ABL intermediate form)

VHDL has defeated KARL around 1990 (see Cadence CEO's comment)

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KARL Licensee Sites

(1981 - 1988)

1.   Dr. Halang, Coca Cola Corp., Essen, Germany,
2.   Prof. Besslich, University of Bremen, Germany,
3.   Prof. Dr. Werner Grass, University of Hamburg, Germany,
4.   Prof. Maria Giovanna Sami, Politecnico di Milano, Italy,
5.   Mr. Paolo Prinetto, Politecnico di Torino, Italy,
6.   Dr. Alberto di Janni, CSELT, Torino, Italy,
7.   Dr. Amelio Patrucco,  CSELT, Torino, Italy,
8.   Mr. M.W. Gill, ITT Corp., Harlow, UK,
9.   Werner Konrad, Techn. University of Munich, Germany,
10. Mr. Gunnar Carlstedt, HYLAB Corp., Goeteborg, Sweden,
11. Mr. Steve Shapiro, AMD Corp., Santa Clara, USA,
12. Prof. Mucha, University of Hannover, Germany,
13. Frank Schmidtke, Siemens Corp., Munich, Germany,
14. Prof. Piloty, Techn University of Darmstadt, Germany,
15. Dr. Modotti, Olivetti Corp., Ivrea, Italy,
      Dr. Giancarlo Toppi, Olivetti Corp., Ivrea, Italy,
      Mr. Morpurgo Segre,  Olivetti Corp., Ivrea, Italy,
16. Dr. P. Pirsch, University of Hannover, Germany,
17. Dr. G. Woysch, Standard Electric Corp., Stuttgart, Germany: (see user feedback )
18. Prof. Geisselhardt, University of Dortmund, Germany,
19. Mr. Eduardo da Costa, TELEBRAS Corp., Campinas, Brasil,
20. P. G. Jensen, Techn. Hogeschool Twente, Enschede, Netherlands,
21. Mr. Wilhelm Haller, University of Stuttgart, Germany,
22. Mr. H. A. Vink, Techn. Hogeschool  Delft, Netherlands,
23. Prof. Dan McCarthy, Trinity College, Dublin, Ireland,
24. Mr. Helmer, GMD Bonn, Schloss Birlinghoven, Germany,
      Mr. Puettmann, GMD Bonn, Schloss Birlinghoven, Germany,
25. Mr. Sebastian Wendlinger PCS Peripheral Computer Systems Corp., Munich, Germany,
26. Dr. P. Schoellkopf, University of Grenoble, France,
      Prof. F. Anceau, University of Grenoble, France,
27. Prof. Eamonn McQuade, National Institute for Higher Education, Limerick, Ireland
28. Mr. Larry L. Kinney, University of Minnesota, Minneapolis, USA,
29. Dr. D. F. Frost, University of Stellenbosch, South Africa,
30. Prof. Barke, University of Hannover, Germany,
31. Dr. A. Hunger, RWTH, Techn. University of Aachen, Germany,
      Prof. Dr. Hans Joerg Tafel, RWTH, Techn. University of Aachen, Germany,
32. Dr. Livio Bruno, Telespazio Corp., Roma, Italy,
33. Prof. Dr. Utz Baitinger, University of Karlsruhe, Germany,
      Mr. Lohmann, Univ. Karlsruhe, Germany,
      Mr. M. Schaefer,  University of Karlsruhe, Germany,
34. Prof. Dr. Kurt Antreich, Techn. University of Munich, Germany,
      Dr. B. Finkbein, Techn. University of Munich, Germany,
35. Prof. Dr. Herzog, University of Erlangen-Nuremberg, Germany,
      Dr. Rainer Klar, University of Erlangen-Nuremberg, Germany,
36. Prof. Dr. M. Boar, University of Bologna, Italy,
      Mr. Giorgio Bacarani, University of Bologna, Italy,
37. Prof. Filipo Sorbello, University of Palermo, Italy,
      Prof. Dr. G. Zito, University of Palermo, Italy,
38. Prof. Dr. H. U. Lemke, Techn. University of Berlin, Germany,
      Mr. Winfried Wacker, Techn. University of Berlin, Germany,
39. Mrs. Mary Sheeran, Oxford University, Oxford, UK,
40. Dr. Bryan Coghlan, University of Western Australia, Perth, Australia,
41. Dr. G. Barbagelata, ELSAG Corp., Genova, Italy,
42. Dipl.-Ing Kaempf, Ernst Leitz Wetzlar GmbH, Wetzlar, Germany,
43. Prof. Dr. Werner Grass, University of Passau, Germany,
44. Mr. Helmut Hahn, Fraunhofer Institut IMG, Duisburg, Germany,
45. Dr. Kunze, TELENORMA Corp., Frankfurt, Germany,
46. Prof. Sung, University of Karlsruhe, Germany,
47. Hartmut Wendt, FTZ of German Bundespost, Darmstadt, Germany,
48. J. Pierre Tual, CII Honeywell Bull, Les Clayes sur Bois, France,
49. Dr. Erich Barke, Siemens Corp., Munich, Germany,
50. Prof. Dr. Baumann, ETH Zuerich, Switzerland,
51. Mr. Per Werner, C.E.R.N. Research Center, Geneva, Switzerland,
52. Dr. Nicolae, EMBL / DESY, Hamburg, Germany,
53. Dr.-Ing. G. Gorla, Italtel Corp., Castello di Settimo Milanese, Italy,
54. Prof. Dr. U. Golze, University of Brauschweig, Germany,
55. EUROSIL GmbH, Eching, Germany,
56. Mr. Shunsuke Miyamoto, Hitachi Ltd., Tokyo, Japan,
57. Prof. Dr. R. Lauber, Univ. Stuttgart, Germany,
58. Mr. Axel Kemper, University of Hannover, Germany,
59. Prof. T. S. Papatheodoru, CTI, University of Patras, Greece,
60. Dr. Theo Vierhaus, GMD Bonn, Schloss Birlinghoven, Germany,
61. Yong Seok Shin, ETRI, Chung-Nam, Korea,
62. Mr. Carlos A. Lopez Barrio, University of Madrid, Spain,
63. Prof. Antonio Nunez-Ordonez, University of Las Palmas, Gran Canaria, Spain,
64. Prof. Dr. Otto Manck, Techn University of Berlin, Germany,
65. Dr. Herbert Gruenbacher, AMI, Unterpremstaetten, Austria,
66. Prof. Mario Salerno, University of Rome at Tor Vergata, Rome, Italy,
67. Dr. Luigi Germanetto, Istituto Giorgio Quazza, Torino, Italy,
68. Prof. C. Halatsis, University of Thessaloniki, Greece,
69. Mrs. Monique Hyvernaud, Alcatel, Les Ulis, France,
70. Centre Suisse d'Electronique et Microelectronque, Neuchatel, Switzerland
71. Dr. Wiekhorst, FGAN e. V., Wachtberg-Werthhoven, Germany,
      Mr. Heger, FGAN e. V., Wachtberg-Werthhoven, Germany,
72. Mr. Klaus Kirchner, FGAN e. V., Dept. QSP, Wachtberg-Werthhoven, Germany,
73. Mr. Carlos I. Z. Mammana, CTI Centro Technologica para Informatica, Campinas, Brasil,
74. ITA, Inst. Technologica para Informatica, Sao Jose dos Campos, Brasil,
75. Prof. Roberto Tom Price, Univ. Fed. di Rio Grande do Sul, Porto Allegre, Brasil,
76. Prof. Eber-Schmitz, Federal University of Rio de Janeiro, Brasil,
77. PUC Catholic University, of Rio de Janeiro, Brasil,
78. Dr. K. Singer, ELTEC Elektronik Corp., Mainz, Germany,
79. Mr. Geoffrey Collis, University of Manchester, UK,
80. Dr. Eugenio Villar, Universidad de Cantabria, Santander, Spain,
81. ITAUcom, Sao Paolo, Brasil
82. Mr. Markus Kohn, Wuppertal, Germany,
83. Prof. Dr. B. Hoefflinger, IMS, University of Stuttgart, Germany,
84. Mr. Heinz Salzmann, Intermetall Corp., Freiburg, Germany,
85. Prof. Dr. Paul Debefre, EPFL, Lausanne, Switzerland,
86. Dirk Goetze, IBM Deutschland Corp., Stuttgart, Germany,
87. see no. 68
88. Mr. Martin, Inst. f. Informatik, University of Stuttgart, Germany,
89. see no. 63
90. Dr. E. L. Moore, ANACAD Computer Systems GmbH, Bonn, Germany,
91. Mr. Xie Zhilang, Shanghai Jiao Tong University, Shanghai, P. R. China,
92. Mr. Daniel Marre, Inst. National des Sciences Appliquees, Toulouse, France,
93. Prof. Dr. D. R. Smith, SUNY, Stonybrook, USA,


Early textual KARL-II implementation package:

(KARL-I, used by the book published in 1977 has not been fully implemented)
 




 

KARL language versions


Software interfaced to KARL, ABLED and RTcode (RTcode is the KARL intermediate form)

A number of CAD programs from other sources have been interfaced to the KARL and ABLED systems: mainly within the CVT and CVS projects.
  1. ABLED (editor / RTL design capture), CSELT, Torino, Italy / University of Kaiserslautern, Germany
  2. ABL2KARL translator; Kaiserslautern University
  3. ARIANNA (interactive chip floor plan generator), CSELT, Torino, Italy
  4. CFSM/ASMA  (algorithmic state machine assembly), CSELT, Torino, Italy
  5. ASMA editor (editor and preprocessor), CSELT, Torino, Italy
  6. BAT (behavioural automatic tester), Politecnico di Torino, Italy
  7. BMIN (logic minimizer), University of Bremen, Germany
  8. COSMIC (Common Storage Manager for IC Designs), CNET, Meylan, Grenoble, France
  9. DTSV (Design and Testing Support for VLSI), Standard Elektrik Lorenz AG, Stuttgart, Germany
  10. FERT (fault model extractor), Olivetti SpA, Ivrea, Italy
  11. FLAP (MOS layout generator for PLAs), University of Genova, Italy
  12. FOLD (for PLA folding), Politecnico di Milano, Italy
  13. hyFi (hyperKarl filter program); Kaiserslautern University
  14. KARATE (KARL Automatic Test Extractor); Kaiserslautern University
  15. KARL compiler; Kaiserslautern University
  16. KARL editor; Kaiserslautern University
  17. KARL simulator; Kaiserslautern University
  18. KMIN (for logic minimization), University of Karlsruhe
  19. MLED (Multi-level editor) Kaiserslautern University
  20. OTAKA (Olivetti Testability Analyser based on KARL), Olivetti SpA, Ivrea, Italy
  21. OFGKA  (Olivetti Fault Generator based on KARL), Olivetti SpA, Ivrea, Italy
  22. OFSKA (Olivetti Fault Simulator based on KARL), Olivetti SpA, Ivrea, Italy
  23. PLA2KARL translator; Kaiserslautern University / CSELT, Torino, Italy
  24. REX (Register Transfer Extractor); Kaiserslautern University
  25. PRIMITIVE (Program for Interactive Microprogram Transformation and its Verification); Passau University, Passau, Germany (Prof. Grass), 1985
  26. SCIL editor (SCIL: Simulator Control and I/O Language); Kaiserslautern University
  27. SCOD (for state encoding), CSELT, Torino, Italy
  28. TIGER (test pattern interactive generation environment), Olivetti SpA, Ivrea, Italy
  29. VERENA (Program for Verification of RT Structures); Passau University, Passau, Germany (Prof. Grass) 1985

Other KARL related software or KARL Dialects


Mainly from foreign sources:

  1. ABLED (interactive graphic design capture and editor), CSELT, Torino, italy / University of Kaiserslautern, Germany, 1985
  2. BACH (Behavioural-Level Automated Compilation and logic optimization), CVS_BK-based;  CVS project; CSELT, Torino, Italy, 1988
  3. CVS-BK; (procedural extension of the KARL language), CVS project; Grenoble, France / Kaiserslautern, Germany / Torino, Italy, 1984
  4. IRENE; (a KARL dialect)  Prof. Francois Anceau, ENSIMAG; Grenoble, France, 1986
  5. KARENE; (a KARL dialect) Prof. Francois Anceau, ENSIMAG; Grenoble, France, 1984
  6. KARL compiler; Prof. Mariagionvanna Sami, Politecnico di Milano, Italy,  1977
  7. Parser for KARL 2; Dr. Ulf Hedengran, Royal Institute of Technology, Stockholm, Sweden, 1980
  8. PSICO  (Behavioural-Level Automated Compilation and logic optimization), based on KARL-3; CSELT, Torino, Italy, 1986
  9. SMART, SiMulator At Register Transfer level; CSELT, Torino, Italy, 1987
  10. N. N., a Layout Module Generator Generator, based on a KARL-3 subset; University of Kyoto, Kyoto, Japan, 1992  (Prof. Moshnyaga and Prof. Yasuura)
From Kaiserslautern only:
  1. hyperKARL; (a KARL extension implemented by a filter program), University of Kaiserslautern, Germany, 1985
  2. IGSIC an interactive graphical Silicon Compiler; Prof. Ewald von Puttkamer, University of Kaiserslautern, 1985
  3. KARL-III; University of Kaiserslautern, Germany, 1984
  4. SIC System (core of a Silicon Compiler), Prof. Ewald von Puttkamer, University of Kaiserslautern, 1985
  5. super KARL;  (a KARL extension implemented by a filter program in front of the KARL compiler), University of Kaiserslautern, Germany, 1987

  6. SYS3 (systolic array synthesis program generating KARL-3 descriptions from KARL-3 descriptions); University of Kaiserslautern, 1989

Studies including KARL

  1. University of Trondheim, Norway, 1978
  2. Politecnico di Torino, Italy, 1985
  3. University of Kaiserslautern, Germany, 1986
  4. ENSIMAG, Grenoble, France, 1984

Major designs implemented in using KARL and ABLED

    Speech Synthesizer;
    The chip was designed at CSELT, Torino, Italy 1986  --
    The chip was fabricated at STmicroelectronics, Agrate Brianza, Italy, in 1986

KARL-related Quotation Index

(Literature from authors outside Kaiserslautern on KARL, ABL, CVS_BK and its Applications, or, referencing such Literature from Kaiserslautern)
Last update (2 exceptions): 1992
  1. P. Haselmeier: The KARL language compiler; report no. 77-14; Instituto di Elettronica, Politechnco di Milano, Milano, Italy, 1977
  2. P. A. Anderson, M. Nygaard: A study of different languages for description and simulation of digitalsystems; report no. 6/78. Univ. Trondheim, CS Division, Trondheim, Norway, 1978
  3. H. Hedengran: A Parser for KARL 2, internal report; Dept. of Applied Electronics, The Royal Inst. of Technology, Stockholm, Sweden, 1980
  4. M. Breuer, R. Hartenstein: Computer Hardware Description Languages and their Applications; North Holland, Amsterdam/New York, 1981
  5. G. Girardi: ABL editor: cell definition CVT-report; CSELT, Torino, Italy; Jan. 1984
  6. G. Girardi: ABL data structure; CVT-report; CSELT, Torino, Italy, March 1984
  7. G. Girardi: ABL editor: user manual (draft); CSELT, Torino, Italy, July 1984
  8. H. Baessmann: Architektur und Mikroprogrammierung von Rechnersystemen mit Hilfe der Register-Transfer-Sprache KARL-II; Diplom-arbeit; University of Bremen, 1984
  9. M. Bedina, F. Distante: On SW development of a Petri Net model for VLSI functional test, CVT report, Politecnico di Milano, Italy, 1984
  10. F. Ferrara, G.Rosenga: Translation of RT Hardware Description into Propositional Logic Representation, CVT rep; CSELT, Torino, 1984
  11. P. G. Bosco, G. Giandonato, E. Giovanetti: Verification of Hardware Descriptions against Temporal Logic Specifications; CVT report; CSELT, Torino, Italy, 1984
  12. C.Segre, S. Morpurgo: Proposed Algorithm for a Testability Analysis Tool based on KARL (CVTOTAKA); CVT report, Ing.Olivetti S.p.A.,Ivrea,Italy, 1984
  13. C.Segre, S. Morpurgo: Olivetti Fault Simulator For RT-Level (KARL) Described Nets; CVT report, Ing.Olivetti S.p.A.,Ivrea,Italy, 1984
  14. C.Segre, S. Morpurgo: Olivetti's Fault Generator For RT-Level (KARL) Described Nets (CVTOFGKA): User manual; CVT report, Ing.Olivetti S.p.A.,Ivrea,Italy, 1984
  15. C.Segre, S. Morpurgo: Olivetti's Fault Simulator For RT-Level (KARL) Described Nets (CVTOFSKA): User manual; CVT report, Ing.Olivetti S.p.A.,Ivrea,Italy, 1984
  16. G. Girardi: CVT-KARENE System-ABLED: Graphic Editor at Register Transfer Level; CVT report; CSELT, Torino, Italy, 1984
  17. N. N.: Specification of the CVT KARENE System; IMAG, Grenoble, 1984
  18. S. Marine, G. Girardi, A. Zappalorto: Draft proposal for the final definition of mixing behaviour and structure in CVT KARENE system; CVT report; IMAG, Grenoble, France / CSELT, Torino, Italy, 1984
  19. W. Grass, N. Erstellung eines Programms zur automatischen Verifikation
  20. 19.W. Grass, N. Schielow*: Automatic Verification of logic Designs; Informatik-Fachberichte 84;  Springer-Verlag, 1984, p.113-126
  21. M. Melgara, M. Paolini, R. Roncella, S. Morpurgo:CVT-FERT: Automatic generator of analytical faults at RT level from electrical and topological descriptions; Int'l Test Conf., Philadelphia, USA, 1984
  22. N.N.: CVT-TIGER: Algorithms and Tool Description; CSELT, Torino, Italy, 1985
  23. C.Segre, S. Morpurgo: The Olivetti Fault Simulator For RT-Level (KARL) Described Nets: User's Manual; CVT report, Ing.Olivetti S.p.A.,Ivrea,Italy, 1985
  24. C.Segre, S. Morpurgo: The Olivetti Fault Generator For RT-Level (KARL) Described Nets (CVTOFGKA): User's  Manual; CVT report, Ing.Olivetti S.p.A.,Ivrea,Italy, 1985
  25. A.Pawlak: A Tutorial Guide to Modern Hardware Description and Design Languages; EUROMICRO Symposium, Brussels, Belgium, 1985
  26. G. Girardi, R. Hartenstein, U. Welters: ABLED - a RT Level Schematic Editor and Simulator User Interface; CVT rep, Kaiserslautern, 1985
  27. S. Morpurgo, A. Hunger, M. Melgara, C. Segre: RTL Validation of VLSI: An Integrated Set of Tools for KARL; IFIP Int'l Symposium on Computer Hardware Description Languages, (CHDL'85); Tokyo, Japan, 1985
  28. W. Grass, N. Schielow: Verena: A Program for automatic verifications of the register transfer description; IFIP Int`l Symp. CHDL`85; Tokyo, Japan, 1985
  29. N.N.: CVT fault generator and simulator level on KARL description nets; CVT report, Ing. Olivetti S.p.A., Ivrea, Italy, 1985
  30. G. Girardi, A. Zappalorto: An experiment on designing with KARENE; the behavioural level; CVT report, CSELT, Torino, Italy, 1985
  31. I. Stamelos, M. Melgara: CVT TIGER: a RT-level Test Pattern Generation and Validation Environment; report, CSELT/Univ. of Thessaloniki/Olivetti, Torino, Italy, 1985
  32. S. Morpurgo, C. Segre: Fault Simulation, at Register Transfer Level, of VLSI; Olivetti Research and Technology Review 3, 1985
  33. P. Prinetto, M. Siviero, V. Vercellone: Progretto di un sistema di elaborazione microprogrammabile: BENC83; Politecnico di Torino, Torino, Italy, 1985
  34. P. Prinetto, M. Siviero: Descrizione e simulazione in ART* e KARL II del multiplicatore TRW MPY 24-MJ; Politecnico di Torino, Torino, Italy, 1985
  35. P. Prinetto, M. Siviero: Analisi comparata dei sistemi di simulazione ART* e KARL II; Politecnico di Torino, Torino, Italy, 1985
  36. Grass,W., Rauscher, R.: A Practicable Strategy for the Verification of Interactive Microprogram Transformations, EUROMICRO 1085, Brussels, Belgium, by North Holland Publishing Co., 1985
  37. M. Rauscher, W. Grass: Experiences in Using KARL in PRIMITIVE (Program for Interactive Microprogram Transformation and its Verification); ABAKUS workshop; Passau, 1986
  38. M. Schielow, W. Grass: KARL Use in VERENA (Verification of RT Structures); ABAKUS workshop; Passau, Germany, 1986
  39. G. Girardi, U. Welters: A Graphic RT-level Editor based on the KARL Compiler Interface; ABAKUS workshop; Passau, Germany, 1986
  40. M. Melgara: A User-Assisted Test Pattern Generator and Validation Environment based on KARL; ABAKUS workshop; Passau, 1986
  41. D. Farelly: The Practical Application of ABLED and KARL in Designing a Speech Synthesizer; ABAKUS workshop; Passau 1986
  42. C. Whiting The CVS Logic Optimizer; ESPRIT Project Discussion Paper; British Telecom, Ipswich, UK, June 1986
  43. G. P. Balboni, V. Vercellone: Experiences in Using KARL-III in Designing a CMOS Circuit for Packet-Switched Networks; ABAKUS workshop; Passau, Germany, 1986
  44. L. Lavagno, R. Munione: Automatic Layout Generation from (KARL) RT Level Descriptions; ABAKUS workshop; Passau, Germany, 1986
  45. S. Marine: IRENE un Langage pour la description, simulation et synthèse automatique du matériel VLSI; diss., INPG, Grenoble, France, 1986
  46. N.N.: CVT software catalogue; CSELT, Torino, Italy, 1986
  47. G.Arato, R. Manione: PSICO: a System for Automatic Layout Synthesis; CSELT, Torino, Italy, 1986
  48. I. Stamelos, M. Melgara, M. Paolini, S. Morpurgo, C. Segre: A Multi-Level Test Pattern Generation and Validation Environment; International Test Conference, 1986
  49. Rauscher, R.: A practicalbe method for interactive Microprogram Transformation and their automatic formal verification; Dissertation, University of Hamburg, 1986
  50. A. Butterfield: From KARL to CIF - Automatic Conversion of High-Level RT Descriptions to an Equivalent High-Level Layout Description; internal report, CS Dept.,Trinity College, Dublin, Ireland, 1986
  51. D. McCarthy: KARL as a Laboratory Instrument in Tertiary Computer Science Courses; internal report, CS Dept.,Trinity College, Dublin, Ireland 1986
  52. Ph. Besslich, H. Baessmann: User manual for the Register Transfer Language KARL-II; Ber. FB-1, WE "Theoretische Elektrotechnik und Digitale Systeme", Fachgeb. Digitaltechnik und Schaltwerksentwurf; University of Bremem, 1986
  53. N. N.: ABAKUS workshop Passau, Germany, June 17 - 20, 1986 - Collection of Viewgraphs; Passau / Kaiserslautern, August 1986
  54. G. Girardi, R. Hartenstein: ABLED - ein CAD-Werkzeug f. den Entwurf von Digitalsystemen; DECUS Munich Symposium, Stuttgart 1986
  55. W. Grass, R. Rauscher: CAMILOD - A Program System for Designing Digital Hardware with Proven Correctness; in (ed. D. Borrione): Proc IFIP Workg Conf. "From HDL Descriptions to Guaranteed Correct Circuit Designs"; Grenoble, France, Sept 1986
  56. A. Pepe: The Verification of Temporal Properties in RTL Descriptions: an Experimental System; internal rep; CSELT, Torino, Italy, 1986
  57. L. Lavagno, R. Manione: Register Transfer to Layout Synthesis using enhanced Standard / Macro Cell Architecture; internal report; CSELT, Torino, Italy, 1986
  58. I. Stamelos, M. Melgara, M. Paolini, S. Morpurgo, C. Segre: A Multi-Level Test Pattern Generation and Validation Environment; Int'l Test Conf. 1986
  59. H. Baessmann, Ph. Besslich: A Macroassembler for the Register Transfer Language KARL-II; report 1/86; F.B. Elektrotechnik, University of Bremen, 1986
  60. Ph. Besslich, H. Baessmann: Simulation of microprogrammable Hardware Structures with  KARL-II; report no. 2/86; F.B. Elektrotechnik, University of Bremen, 1986
  61. N. N.: Monitor User's Manual; CVT report, CSELT, Torino, Italy, 1986
  62. N. N.: Testing Tools for RT level (KARL) described nets: User Manual; CVT report; Olivetti, Ivrea, Italy, 1986
  63. N. N.: Olivetti testability analysis tools based on KARL; CVT report; Olivetti, Ivrea, Italy, 1986
  64. N. N.: Validation tools at different levels and combined testing: final report; CVT report, RWTH Aachen, 1986
  65. F. R. Wagner, C. M. Freitas,L. G. Colendziner: Equivalencia de Descrições Textuais de Gráficas de Sistemas Digitais num Anbiente de CAD; Seminario Integrado de Software a Hardware XIII, Recife, PE (Brazil), July 1986, Anais, UFPe, 1986, p. 486-493
  66. F. R. Wagner, C. M. Freitas, L. G. Colendziner, F. M. Oliveira, L. F. R. Machado: Modelagem Automatizada a Nível RT de Circuito; Seminario Integrado de Software a Hardware XIII, Recife, PE (Brazil), July 1986, Anais, UFPe, 1986
  67. F. R. Wagner, C. M. Freitas, L. G. Colendziner, F. M. Oliveira, L. F. R. Machado:, Metodologia de Projeto de Sistemas Digitais num Ambientede CAD; Seminario Integrado de Software a Hardware XIV, Salvador, BA(Brazil), 1987, Anais, UFPe, 1986, p. 131-141
  68. Buschke, W. Grass, W. Rauscher, R.: BOSS - A Functional Block Oriented Intermediate Language for RT-Level Hardware Descriptions; EUROMICRO 1986, Venice, Italy, September 1986, in:: Microprocessing and Microprogramming, North Holland, Amsterdam, 1986
  69. A. Butterfield, D. P. McCarthy: Teaching the Use of KARL for Customer / Supplier Interface Applications; Proc. European Conference on Customer/Vendor Interfaces in Microelectronics, Kaiserslautern, Sept 23/24, 1986; GMD Lecture Notes, St. Augustin, Germany, 1987
  70. N. Schielow*: Implementation of a program for automatic verification of hierarchical refinements on datapath descriptions at RT level and gate level; Diplomarbeit, Fachbereich Informatik, University of Hamburg, 1987
  71. A. Bonomo, G. Bussolino, G. Girardi, M. Italiano: From Structured RT Description to Floor-Plan; internal report; CSELT, Torino, Italy, 1986 - also: EUROMICRO Symposium, Portsmouth, UK, 1987
  72. L. Lavagno, R. Manione: SMART, SiMulator At Register Transfer level; internal report, CSELT, Torino, Italy, 1987
  73. L. Lavagno, R. Manione: From Register Transfer to Silicon via Enhanced Standard /MacroCell Architecture; rep, CSELT, Torino Italy 1987
  74. A. Bonomo, G. Girardi, L. Lavagno, R. Hartenstein, R. Hauck: . Syntax Diagrams of the CVS_BK Language (CVS Behavioural Karl); ESPRIT / CVS report, CSELT, Torino, Italy / Informatics Dept., Univ. Kaiserslautern 1987
  75. A. Bonomo, G. Girardi, L. Lavagno, R. Hartenstein, R. Hauck: Semantic Specification of CVS_BK Language (CVS Behavioural Karl); ESPRIT / CVS report, CSELT, Torino, Italy /Informatics Dept., Univ. Kaiserslautern, 1987
  76. G. Girardi, S. Giorcelli, G. Giandonato, The HDL Subsystem of an Integrated CAD System, in: R. W. Hartenstein, Hardware Description Languages, Advances in CAD for VLSI, Volume 7, North Holland, Amsterdam/New York/Oxford/Tokyo, 1987, pp. 375-406
  77. F. R. Wagner et al.: A Digital System Design Methodology Based on Nets of Agents; Proc. IFIP CHDL'87 - Symp. on Computer Hardware Description Languages and their Applications; North Holland, Amsterdam, 1987
  78. K. Haimann: Design and Simulation of microprogrammable computerw with the Computer Hardware Descriptive Language KARL-III; Diplomarbeit Nr. 513, Informatik, University of Stuttgart, Nov. 1987
  79. F. R. Wagner, C. M. Freitas, L.G. Colendziner, F.M. Oliveira, L. F. R. Machado: Linguagens de Descrição do Processo de Projeto em AMPLO; Porto Allegre, RGS (Brazil), CPGCC- URGS, March 1987, 17 p., Relatorio de Pesquisa 66 (research report no. 66)
  80. N.N.: Efficiency of validation tools at different levels; CVT report, RWTH Aachen, 1985
  81. A. Pawlak: HL Design Tools - The E.I.S. Perspective; E.I.S. Workshop, GMD Schloss Birlinghoven, Oct. 1987
  82. A. Pawlak: Report on the CHDL'87 Conference at Amsterdam, April 27 - 29, 1987; E.I.S. Workshop, GMD Schloss Birlinghoven, Oct. 1987
  83. A. Pawlak: Lecture Notes on Hardware Description Languages - GMD Lecture Notes; Arbeitspapiere der GMD, No. 255, GMD Schloss Birlinghoven, July 1987
  84. F. R. Wagner, C. M. Freitas,L. G. Colendziner: The AMPLO System: An Integrated Environment for Digital System Design; IFIP Workshop on Tool Integration and Design Environments; Paderborn, Germany, Nov. 1987, North Holland Publishing Co., Amsterdam, 1987
  85. F. R. Wagner: KAPA - Una Linguagem para e Descrição de Hardware no Nivel de Transferencia entre Registrados; Porto Allegre, RGS (Brazil), CPGCC - UGermanyS, April 1987, 40 p., Relatorio de Pesquisa 68 (research rep. no. 68)
  86. C. M. Dal Sasso-Freitas, F. R. Wagner, F. M. Oliveira: Especificação do Editor Grafico KAPA; Porto Allegre, RGS Brazil), CPGCC UGermanyS, April 1987, 62 p., Relatorio de Pesquisa 68 (research rep. no. 62)
  87. R. Rauscher, J. Westendorf: A System for Verification of Interactive Microprogram Transformations; EUROMICRO Symposium, Ports-mouth, UK, Sept, 1987
  88. K. Haimann: Entwurf und Simulation mikroprogrammierter Rechner mit der Hardware- Beschreibungssprache KARL-3; Diplomarbeit, Institut fuer Informatik, Univ. Stuttgart, 1987
  89. T. Ohtsuki (Series Editor): Advances in CAD for VLSI; North Holland Publishing Co. New York, Amsterdam, Oxford, Tokyo, 1987
  90. W. Fichtner, M. Morf: VLSI CAD Tools and Applications; Kluwer, Boston, 1987
  91. Rauscher, R. Westendorf, J.: A System for Verification of Interactive Microprogram Transformations; EUROMICRO 1987, Portsmouth, UK, in: Microprocessing and Microprogramming, North Holland, Amsterdam, 1987
  92. Rauscher, R.:Benutzerhandbuch und Dolumentation zu PRIMITIVE. Mitteilung 151 des Fachbereich Informatik, University of Hamburg, 1987
  93. A. Hunger, M. Melgara, S. Morpurgo, C. Segre: Register Transfer level validation of VLSI; CSELT Technical reports, vol 14, no. 1, Torino, Italy, Febr. 1988
  94. A. Pawlak: Standards in design automation versus KARL/ABL design environment (Invited Paper); Proc. 2nd ABAKUS workshop, Innsbruck, Austria, Sept. 1988
  95. W. Grass: VERENA - A.CAD-tool.for.designing guaranteed.correct.logic.circuits;Proc.2nd ABA-KUS workshop, Innsbruck, Austria, Sept  1988
  96. M. Mutz: Logic Verification based on function graphs; Proc. 2nd ABAKUS workshop, Innsbruck, Austria, Sept. 1988
  97. K. Jansen: Transformations of RT-descriptions guided by features of logic implementations to be verified; Proc. 2nd ABAKUS workshop, Innsbruck, Austria, Sept. 1988
  98. A. Bonomo, M. Italiano, L. Lavagno, L. Maggiuli, M. Melgara, M. Paolini, I. Stamelos: Easily testable data part synthesis in the BACH silicon compiler; Proc. 2nd ABAKUS workshop, Innsbruck, Austria, Sept. 1988
  99. A. Bonomo, L. Lavagno, L.: Control part synthesis in the BACH silicon compiler; Proc. 2nd ABAKUS workshop, Innsbruck, Austr Sep 1988
  100. A. Bonomo, G. Girardi, A. Lecce, L. Maggiulli: GENMON: a specialized ABL editor for design methodology descriptions; Proc.2nd ABA-KUS workshop, Innsbruck, Austria, Sept. 1988
  101. S. Rust: An experimental system design environment for chip design; Proc. 2nd ABAKUS workshop, Innsbruck, Austria, Sept. 1988
  102. D. Maertens: Special Problems of the event driven simulation stragtegy; Proc. 2nd ABAKUS workshop, Innsbruck, Austria, 1988
  103. Rauscher, R.: Analysis of design methodologies for digital systems; Proc. 2nd ABAKUS workshop, Innsbruck, Austria, Sept. 1988
  104. A. Jaime, E. Villar: SECUENTEST: Automatic generation of checking experiments for sequential machines; Proc. 2nd ABAKUS workshop, Innsbruck, Austria, Sept. 1988
  105. Cecinati, R., Fossati, R., Licciardi, L., Pacchiotti, A., Paolini, M.: The use of KARL III in the RIPAC chip design; Proc. 2nd ABAKUS workshop, Innsbruck, Austria, Sept. 1988
  106. Donati,N.,Fatini,N.: Experience on CVS-BK use on a signal processor circuit; Proc. 2nd ABAKUS workshop, Innsbruck, Austria,1988
  107. A. Bonomo, M. Italiano, L. Lavagno, L. Maggiuli, M. Melgara, M. Paolini, I. Stamelos: BACH (Behavioural-Level Automated Compilation of Hardware): An Integrated ASIC Synthesis System; ESPRIT Technical Week, Brussels, Belgium 1988
  108. J. Darringer, F. J. Rammig: Computer Hardware Description Languages and their Applications; North Holland, Amsterdam, 1990
  109. A. Balboni, V. Rampa, S. Ravaglia: Comparative Evaluation of Automatic vs. manual Design for an Application-specific DSP; ESPRIIT Conference, Nov.1991, Brussels, Belgium
  110. G. Roos, E. Bernath, T. Buechner, S. Rust, T. Schwederski: Dedicated VLSI Processors for Image Processing; GME-Conference on VLSI; Baden-Baden 1991; VDE-Verlag, Berlin, 1991
  111. V. G. Moshnyaga, H. Onodera, K. Tamaru, H. Yasuura: A Language for Designing Data-Path Module Generators; Int’l Design Workshop "Russian Workshop’92", Moscow, Russia
  112. V. G. Moshnyaga, H. Yasuura: A Data-Path Modules Design from Algorithmic Representations; IFIP WG 10.5 Workshop on Synthesis, Generation and Portability of Library Blocks for ASIC Design, Grenoble, France, Mar 1992
  113. V. G. Moshnyaga, H. Yasuura: A Language for Designing Module Generators; Proc. SASIMI’92 - Synthesis and Simulation Meeting and Int’l Exchange, Kobe, Japan, Apr. 1992
  114. Kees G. W. Goossens: Embedding Hardware Description Languages in Proof Systems; Doctor of Philosophy (Ph. D. thesis) , University of Edinburgh, 1992
  115. M. Vieillot: Mise en oeuvre de l'opérateur Gamma à l'aide de circuits logiques reconfigurables; Thèse, Présentée devant l'Université de Rennes 1, Institut de Formation Supérieure en Informatique et Communication, Pour obtenir Le Titre de Docteur de l'Université de Rennes 1, Mention Informatique, le 2 février 1996
  116. P. Le Moënner: Contribution à la réalisation d'une chaîne complète pour la synthèse de circuits réguliers; Thèse, Présentée devant l'Université de Rennes 1, pour obtenir le grade de : Docteur de l'Université de Rennes 1, Mention Informatique École Doctorale: Sciences Pour l'Ingénieur, le 21 novembre 1997

KARL-related Literature

(Literature on KARL, ABL, CVS_BK and its Applications, published by our group)
 
  1. R. Hartenstein: Fundamentals of Structured Hardware Design: A Design Language Approach at RegisterTransferLevel; North Holland; Amsterdam/New York, 1977.
  2. R. W. Hartenstein, E. von Puttkamer: KARL - a Hardware Description Language as a part of a CAD tool for VLSI; CHDL'79, Int'l Symp. on Computer Hardware Description Languages and their Applications, Palo Alto, California, USA, 1979; IEEE New  York, 1979
  3. R. Hartenstein: Basics of Structured Design Methodologies: Data Paths and Finite State Machines, in (eds.: P. Jespers, C.  Sequin): Design Methodologies for VLSI Circuits; Noordhoff &Stijthoff, Alphen van Rijn), Netherlands, 1981
  4. R.Hartenstein, P.Liell, E.Schaaf: The Grammar of KARL 2; internal report, Kaiserslautern, 1981
  5. R. Hartenstein, P. Liell, E. Schaaf, B. Weber: KARL user manual and introduction; report, Berkeley / Kaiserslautern, 1981
  6. E. Schaaf: PASCAL-Implementierung eines KARLcompiler;Diplomarb.;Kaiserslautern 1981
  7. B. Weber: PASCAL-Implementierung eines Simulators auf KARL-2 Basis; Diplomarbeit; University of Kaiserslautern,1981
  8. M. Breuer, R. Hartenstein: Computer Hardware Description Languages and their Applications; North Holland, Amsterdam/New York, 1981
  9. R.Hartenstein: KARL-II eine Sprache zur Spezifikation beim Entwurf kundenspezifischer Digitalbausteine; Angewandte  Informatik; 12/1982
  10. R. Hartenstein, P. Liell: Specification of the KARL-III language; University of Kaiserslautern, 1983
  11. N. N.: KARL-II Instant; technical report, University of Kaiserslautern, 1983
  12. R. Hartenstein, P. Liell: KARL-II Language Reference Manual, rep, University of Kaiserslautern 1983
  13. R. Hartentstein, A. Mavridis: RTCode Instant; CVT report, University of Kaiserslautern, 1983
  14. R. Hartenstein: Specification of the KARL-III language; CVT rep.; University of Kaiserslautern, 1983
  15. P. Liell: Test Pattern Generation for Data Paths using Iterative Arrays of Cells; Ph.D. Dissertation; University of Kaiserslautern, 1983
  16. A. Sassenhoff*: Core of an interactive graphic Silicon Compilerfor LSI / VLSI esign at Register Transfer Level, Ph.D. dissertation, University of  Kaiserslautern, 1983
  17. H. Mirkes: Simulation of Petri nets using the KARL Language; rep., University of Kaiserslautern, 1983
  18. H. Borrmann: The super KARL filter program; University of Kaiserslautern, 1983
  19. R. Hartenstein: KARL-II application notes; CVT- report; University of Kaiserslautern, 1983
  20. G.Girardi, R.Hartenstein: ABL-Specification -Draft; CVT-rep., Torino/Kaiserslautern, 1983
  21. K. Lemmert: KARL-III grammar - prelimary version; University of Kaiserslautern, Jan. 1984
  22. R. Hartenstein, K. Lemmert: KARL-III reference manual; CVT report, University of Kaiserslautern 1984
  23. A. Wodtko: Semantics Processing within the KARL-III compiler; Diploma-Thesis; University of Kaiserslautern, 1984
  24. K. Lemmert: A LARL(1) Parser of the RT Language KARL-III; Diplarb; University of Kaiserslautern, 1984
  25. B.Borrmann, R.Hartenstein*: Translation of superKarl constructs into the computer hardware descriptive language  KARL; report, University of Kaiserslautern, May 1984
  26. N. N.: KARL-III Instant ; CVT report, University of Kaiserslautern, June 1984
  27. B. Borrmann, R.Hartenstein: Super KARL-III Specification; CVT report, University of Kaiserslautern 1984
  28. U. Welters: ABL2KARL translator:Algorithm description; CVTreport, University of Kaiserslautern 1984
  29. N. N.: KARL-II Hardware Description and Simulation Sessions: a collection of examples; report, University of Kaiserslautern,1984
  30. R. Hartenstein, K. Lemmert*: Conception and Specification of digital Hardware, guided by a Design Language; Proc. 11. Mikroelektronik-Kongress, Munich, 1984
  31. R. Hartenstein, K. Lemmert: A Design Language for the "Long Thin Man": Proposal of a Methodology for Problem Capture and  Conceptual Design; CVT report, University of Kaiserslautern, 1985
  32. R. Hartenstein, A. Wodtko: Automatic Generation of Functional Test Patterns from RT Language Source; internal report; University of  Kaiserslautern, 1985
  33. G. Girardi, R. Hartenstein, U. Welters: ABLED - a RT Level Schematic Editor and Simulator User Interface; CVT rep, University of  Kaiserslautern, 1985
  34. H. Borrmann: hyperKARL-III Language Reference Manual; CVT-report;University of Kaiserslautern, 1985
  35. H. Borrmann*: Design of a Preprocessor for the RT Language  KARL-III; Diplomarbeit (2 volumes); University of  Kaiserslautern, 1985
  36. K. Lemmert: Data Path Descriptions; internal report, University of Kaiserslautern, 1985
  37. U. Welters: Graphic Hardware Description Languages; rep., University of  Kaiserslautern, 1985
  38. A. Mavridis: Languages for Simulator Activation and Test Description; internal report, University of Kaiserslautern, 1985
  39. R. Hartenstein,A Wodtko: Automatic generation of Functional Test Patterns from RT language source; Int'l EUROMICRO  Symposium; Brussels, Belgium, 1985
  40. G.Girardi, R. Hartenstein, U. Welters: ABLED: a RT level Schematic Editor and Simulator user Interface; Int`l EUROMICRO Symposium; Brussels, Belgium, 1985
  41. N. N.: KARL-III Primer (draft), CVT report, University of Kaiserslautern, April 1985
  42. R. Hartenstein et al.: KARL language update, CVT report, University of Kaiserslautern, 1985
  43. R. Hauck: KARL-3 on VAX under VMS/User Guide; CVT report, University of Kaiserslautern, 1985
  44. N. N.: KARL-3 and SCIL condensed grammars for quick reference; University of Kaiserslautern 1985
  45. A. Mavridis: SCIL-3 Grammar (Draft), CVT report, University of Kaiserslautern, July 1985
  46. K. Lemmert: KARL-3 grammar - version July 1985; CVT report, University of Kaiserslautern, 1985
  47. A. Mavridis: RTcode Instant - version July 1985; CVT report, University of Kaiserslautern, 1985
  48. R. Hartenstein, K. Lemmert: The Hardware Description Language KARL-III: its Integration into a CAD Tool Box; report, University of Kaiserslautern 1985
  49. G. Alfs, R. Hartenstein, A. Wodtko: C-Testable Cells for ATPG from RT Descriptions; report; University of Kaiserslautern 1985
  50. R. Hartenstein, A. Wodtko: Functional Test Generation within the KARL-III System; report, University of Kaiserslautern 1985
  51. R. Hartenstein, W. Nebel: EDIF-based Notation for Layout/Circuit Relations: toward Technnology-Independance of CAD Tools;  report; University of Kaiserslautern 1985
  52. E. von Puttkamer*: The SIC System as a core of a Silicon Compiler, report SFB-124 nr. 18/85, University of Kaiserslautern, 1985
  53. Th. Knieriemen*: A Program Generator for the Register Transfer Language KARL- III as a Software Component for a  CAD System, Dipl.-Thesis, University of Kaiserslautern 1985
  54. D. Hartert, Th. Knieriemen*: IGSIC an interactive graphical Silicon Compiler;  report 151/185, Fachbereich Informatik, University of Kaiserslautern, 1985
  55. R. Hartenstein, R. Hauck, A. Hirschbiel: A KARL simulator Physical Model Extension; report, University of Kaiserslautern, 1986
  56. K. Lemmert*: Test-friendly structured Architecture Design for VLSI- Circuits: Guiding the User throug a CAD System; EIS-workshop, Bonn, Germany, 1986
  57. K. Lemmert, W. Nebel: Conceptual Design based on on HDL use; internal report, University of Kaiserslautern, Kaiserslautern, 1986
  58. R. Hartenstein, R. Hauck: Design of Symbolic Layout using RT Level CAD Tools; report, University of Kaiserslautern 1986
  59. R. Hartenstein, W. Nebel: REX: a new CAD Tool shifts Functional Circuit Verification towards RT level; report, University of Kaiserslautern, 1986
  60. R.Hartenstein, R.Hauck*: Design of Symbolic Layout with Register Transfer Level Tools; 2. E.I.S.-Workshop,  Bonn 1986
  61. R. Hartenstein, R. Hauck*: Deriving Behavioural Descriptions from Matrix-oriented Layout; report, University of Kaiserslautern, 1986
  62. R. Hartenstein, R. Hauck: A simple Silicon Synthesizer for MOL circuits; report, University of Kaiserslautern, 1986
  63. R. Hartenstein, R. Hauck: Recursive Cell Declarations in a RT Language; report, University of Kaiserslautern, 1986
  64. K. Lemmert: Steps toward KARL Use as a Design Calculus; ABAKUS workshop; University of Passau 1986
  65. G. Girardi, U. Welters: A Graphic RT-level Editor based on the KARL Compiler Interface; ABAKUS workshop; University of Passau, Germany, 1986
  66. R. Hauck: A General Method for KARL Extraction from Matrix-oriented Layout; ABAKUS workshop; University of Passau, Germany, 1986
  67. R. Hauck: A simple KARL-based Editor for Synthesis and Optimization of MOL (Matrix-oriented Layout); ABAKUS workshop; University of Passau, Germany, 1986
  68. G. Alfs, A. Wodtko: KARL Modelling of C Tests for Data Paths; ABAKUS; University of Passau, 1986
  69. R. Hartenstein Proposal of a High Level Hardware Description Language; ESPRIT / CVS report, University of Kaiserslautern, Sept. 1986
  70. W. Nebel: KARL Extraction from Layout; ABAKUS workshop; Passau, Germany, 1986
  71. R. Hauck, A. Hirschbiel: A Physical Model Extension for KARL Simulators; ABAKUS workshop; Passau, 1986
  72. N. N.: KARL-related software catalogue; Univ. Kaiserslautern, 1986
  73. R. Hartenstein, K. Lemmert: KARL-III Language Reference Manual, ed. March 1986; University of Kaiserslautern,
  74. R. Hauck: KARL-III System V 3.6 Release Notes, CVT report, Univ. Kaiserslautern 1986
  75. U. Welters: ABLED User Manual; report, University of Kaiserslautern 1986
  76. D. Hartert, Th. Knieriemen, E. von Puttkamer*: Das IGSIC-System als CAD-Werkzeug zum Entwurf integrierter Schaltungen, report, University of Kaiserslautern, 1986
  77. H. Kloesel: Implementation of the MLED editor and its application at physical layout level; Diploma thesis; Fachber. Informatik; University of Kaiserslautern; 1986
  78. U. Welters: Specification of the MLED multi-level editor; report, University of Kaiserslautern; 1986
  79. U. Welters: Implementation of an ABL-to-EDIF / EDIF-to-ABL converter; report; Fachbereich Informatik, University of Kaiserslautern, 1986
  80. J. Eiden: Implementation of the MLED editor and its application at symbolic layout level; Diploma thesis; Fachbereich fuer Informatik; University of Kaiserslautern; 1986
  81. R. Hartenstein: A very high level hardware description language, translatable into KARL - Draft; ESPRIT-CVS report, University of Kaiserslautern, 1986
  82. R. Hartenstein, U. Welters: VLSI Design and Simulation at Register Transfer Level; in (eds.: W. Fichtner, M. Morf): Proc. IFIP  Summer School on VLSI Design, Beatenberg Switzerland, 1986; Kluwer , 1986
  83. G. Girardi, R. Hartenstein, U. Welters: ABL - an interactive graphic user interface in microelectronics; in (Hrsg.: J.Encarnaçao): CAD-Schnittstellen und Datentransfer-Formate im Elektronik-Bereich; Springer 1986
  84. R. Hauck, R. Hartenstein: The draft grammar of superKARL-III; internal report, University of Kaiserslautern, 1986
  85. J. Gebhard, R. Hartenstein, R. Hauck, D. Oelke The superKARL-III Language Specification; internal report, University of Kaiserslautern, 1986
  86. R. Hartenstein, A. Mavridis: RT - CODE Instant for KARL-III (new edition) , report, Fachbereich Informatik, University of Kaiserslautern 1986
  87. R. Hartenstein, R. Hauck: The KARL System User Guide; CVT report, Kaiserslautern University, Kaiserslautern, Germany, 1986
  88. R. Hartenstein, K. Lemmert: A CAD Tool Box around a Hardware Descdription Language; EUROMICRO Symp. Venice, 1986, North Holland 1986
  89. N. N. KARL Manual; University of Kaiserslautern, 1986
  90. N. N.: ABAKUS workshop Passau, Germany, June 17 - 20, 1986 - Collection of Viewgraphs; University of Passau / University of Kaiserslautern, August 1986
  91. G. Girardi, R. Hartenstein: ABLED - ein CAD-Werkzeug f. den Entwurf von Digitalsystemen; DECUS Munich Symposium, Stuttgart 1986
  92. R. Hartenstein, U. Welters: Higher Level Simulation and CHDLs; Proc. IFIP Summer School on VLSI Design; Beatenberg,  Switzerld, 1986
  93. W. Nebel: REX - Automatic Extraction of RT-Level Descriptions from Integrated Circuit Layout Data; Dissertation, FB  Informatik, University of Kaiserslautern, 1986
  94. Oelke, D.*: VLSI Design of the Functional Decoder of the  PISA-Address Generator; Projektarbeit, University of Kaiserslautern 1986
  95. Gebhard,J.*: VLSI Design of a Slice of the PISA-Address Generator; Projektarbeit, Un. Kaiserslautern 1986
  96. Ast, A.*: KARL-3 Description of an Image Signal Preprocessor; Projektarbeit, University of Kaiserslautern 1986
  97. .J. Gebhardt, R. Hartenstein, R. Hauck, D. Oelke: Functional Extraction from Personality Matrixes of MOL (Matrix-oriented Logic) circuits; IFIP CHDL'87; North Holland 1987
  98. A. Wodtko: RT Languages in Goal-oriented CAD Algorithms; in (R. Hartenstein, ed.): Hardware Description Languages; Elsevier 1987
  99. K. Lemmert: Data Path Descriptions; in (R. Hartenstein, ed.): Hardware Description Languages; Elsevier , 1987
  100. U. Welters: Graphic Hardware Description Languages; in (R. Hartentein, ed.): Hardware Description Languages; Elsevier, 1987
  101. K. Lemmert, W. Nebel: Conceptual Design based on on HDL use; (R. Hartenstein, ed.): Hardware Description Languages;  Elsevier Scientific, Amsterdam/New York, 1987
  102. A. Mavridis: Languages for Simulator Activation and Test Description; in (R. Hartenstein, ed.): Hardware Description  Languages; Elsevier, 1987
  103. R. W. Hartenstein: Simulation von VLSI-Schaltungen; CAD-CAM REPORT, Febr. 1987
  104. R. Hartenstein, W. Nebel: Shifting Functional Design Verification Towards RT Level by Automatic Register Transfer Net  Extraction; IFIP CHDL'87, Amsterdam, 1987
  105. R. Hartenstein, R. Hauck: Functional Extraction from Personality Matrixes of MOL (Matrix-Oriented Logic) Circuits; IFIP  CHDL'87, Amsterdam, 1987
  106. R. Hartenstein, W. Nebel: Functional Design Verification by Register Transfer Net Extraction from Integrated Circuit Layout Data; Proc. IEEE COMP EURO, Hamburg, 1987
  107. .J. Tretter: Realisierung geometrischer Entwurfs-Beschreibungen in der RT-Ebene durch Cluster-Bildung; Dissertation, Un. Kaiserslautern, 1986
  108. H. Salzmann*: Implementation of a  Technology-independent Circuit Extractor for hierarchical grid-based Layouts; Dipl.-Arbeit; University of Kaiserslautern, 1987
  109. A. Wodtko*: Funktional  Test Pattern Generation from  KARL Descriptions; E.I.S.-Worksh. Bonn 1986
  110. R. Hartenstein: Computer Structure Partitioning Schemes; ESPRIT report, University of Kaiserslautern 1987
  111. B. Hollunder*: Design, Description, and  Verification of a Pocket Calculator using the Language KARL-III; Projektarbeit, FB Informatik, University of Kaiserslautern, Jan. 1987
  112. K. W. Joerg: AMET - ABLED / MLED-to-EDIF Translator; Projektarbeit, FB Informatik, University of Kaiserslautern, Jan. 1987
  113. R. Hartenstein, R. Hauck: A Behavioural / Non-procedural Mixed-Level Simulator for Digital VLSI Systems; ESPRIT / CVS report, CS Dept., University of Kaiserslautern, Febr. 1987
  114. R. Hartenstein, R. Hauck: Simulator Specification for CVS_BK; report, University of Kaiserslautern, Febr. 1987
  115. R.Hartenstein, U.Welters: MLED: A Multiple Abstraction Level Graphical Editor; EUROMICRO'87; Portsmouth; UK, Sept. 1987
  116. R. Hartenstein, U. Welters*: Multi Level Graphic Editor as a DBMS for Simulation Environments; ASIM '87 - 4. Symposium  Simulationstechnik; Zuerich, Switzerland, Sept. 1987
  117. R. Heinen*: Portation of the KARL-III-System onto the Atari 1040 ST; Projektarbeit; Fachber. Informatik, University of Kaiserslautern, 1987
  118. .J. Altmeyer: Portation of the KARL-III-System onto an IBM PC AT; Projektarbeit; Fachbereich Informatik, University of Kaiserslautern; 1987
  119. G. Fischer*: Test Pattern Generation for KARL Primitives using the Test Pattern Generation Program DALGO; Projektarbeit, University of Kaiserslautern, 1987
  120. R. Haack*:  Implementation of a Programm for Input und Hierarchy Control of an RT Extractor; Diplomarbeit, University of Kaiserslautern, 1987
  121. U. Frank*: Implementation of a Programm for Conversion of  EDIF RT Networks into a KARL-3-Description; Diplomarbeit, University of Kaiserslautern, 1987
  122. M. Duhl*: Incremental Development and Description of a Shuffle Sort Array - Circuit in hyperKARL from the Algorithm Representation of the Bubble Sort Algorithm; Projektarb., Informatik, University of Kaiserslautern, 1988
  123. R. Heinen*: Unser Manual for KARL-3 on ATARI - ST; report, Fachbereich Informatik, University of Kaiserslautern, 1987
  124. R. Hartenstein, R. Hauck, K. Lemmert, A. Wodtko: KARL-4 and SCIL-3 Grammar (Draft); ESPRIT / CVS report, Dept. of Computer Science, University of Kaiserslautern, 1987
  125.  K. Bastian*: DEsign and Implementation of an incremental Compiler for SCIL-3 Diplomarbeit, Fb. Informatik, University of Kaiserslautern, 1987
  126. A. Schwarz: Implementierung von Standardfunktionen und Prozeduren fuer SCIL-3; Diplomarbeit, Fb Informatik, University of Kaiserslautern, 1987
  127. A. Mavridis: SCIL-III - A Simulator and Tester Activation Language for VLSI Circuits; Dissertation, Fb Informatik, University of Kaiserslautern, 1987
  128. J. Gebhard*: Sprachdefinition und Implementierung von matrixorientierter Logik in superKARL; Diplomarbeit, Fachbereich Informatik, University of Kaiserslautern, 1987
  129. D. Oelke*: Implementierung der Sprache superKARL; Diplomarbeit, Fachbereich Informatik, University of Kaiserslautern, 1987
  130. R. Hartenstein: Computer Structure Partioning Schemes; ESPRIT / CVS report, Dept of Computer Science, University of Kaiserslautern, 1987
  131. F. R. Wagner et al.: A Digital System DesignA. Pawlak: Report on the CHDL'87 Conference - Amsterdam, April 27 - 29, 1987; E.I.S. Workshop, GMD Schloss Birlinghoven, Oct. 1987
  132. A. Pawlak: Lecture Notes on Hardware Description Languages - Lecture Notes; Arbeitspapiere der GMD, No. 255, GMD Schloss Birlinghoven, July 1987
  133. F. R. Wagner, C. M. Freitas, L. G. Colendziner: The AMPLO System: An Integrated Environment for Digital System Design; IFIP Workshop on Tool Integration and Design Environments; Paderborn, Germany, Nov. 1987, North Holland, 1987
  134. J. Bloedel, R. Hartenstein, W. Nebel, M. Ryba: A Technology Description Method; Proc. EUROMICRO Symp., Portsmouth, UK,  Sept, 1987; North Holland, Amsterdam, 1987
  135. K. Haimann*: Design and Simulation of a microprogrammable Computer using the Computer  Hardware Descriptive Language KARL-3;  Diplomarbeit, Institut fuer Informatik, University of Stuttgart, 1987
  136. Alfs, G.: Design and Implementation of a Heuristic Sea4ch Algorithm for the KARATE System; Diplomarbeit, University of Kaiserslautern, 1987
  137. Bloedel, J.*: PAGE - a ELL(1)-basied EDIF Parser Generator - Analyis Part; Doplomarbeit, University of Kaiserslautern, 1987
  138. Brosowski, J.*: Window Management for the MLED-Graphic System, Dimplomarbeit, University of Kaiserslautern, 1987
  139. R. Hartenstein: Classification of Hardware Description Languages; in [140]
  140. R. Hartenstein (Hrsg.): Hardware Description Languages; Band 7 von [141]
  141. T. Ohtsuki (Series Editor): Advances in CAD for VLSI; North Holland Publishing Co. New York, Amsterdam, Oxford, Tokyo,  1987
  142. R. Hartenstein, U. Welters: Higher Level Simulation and CHSLs; in [143]
  143. W. Fichtner, M. Morf: VLSI CAD Tools and Applications; Kluwer, Boston, 1987
  144. Gimber, J.*: Implementation of a Logic Diagramm-Generator; Diplomarbeit, University of Kaiserslautern, 1987
  145. Rauscher, R. Westendorf, J.: A System for Verification of Interactive Microprogram Transformations; EUROMICRO 1987,  Portsmouth, UK, in: Microprocessing and Microprogramming, North Holland, Amsterdam, 1987
  146. Riedmueller, M.*: Implementation of a Programm for Extraction of RT networks from EDIF circuit descriptions,  Diplomarbeit, University of  Kaiserslautern, 1987
  147. S. Pitiakudis*: Design and Implementation of Algorithms for Analysis and Optimization of RT graphs and for Rault Localization; Diplomarbeit, University of Kaiserslautern, 1987
  148. M. Duhl*: Description and Simulation ausgewaehlter Schaltungsbeispiele in der Sprache superKARL; Diplomarbeit, Informatik, University of Kaiserslautern, 1988
  149. J. Bloedel, R. Hartenstein, W. Nabel, M. Ryba: EDIF Notation for Layout / Circuit Relations; in (ed. F. Rammig): Tool Integration and Design Environments; North Holland, 1988
  150. Alfs, G., Hartenstein, R., Wodtko, A.:The KARL / KARATE System - Automatic Test Pattern Generation Based on RT Level Descriptions; Proceedings ITC - Int'l Test Conference, Sept. 12 - 14, 1988, Washington DC., 1988
  151. Alfs, G., Hartenstein, R., Wodtko, A.: The KARL/KARATE SYstem - Integrating Functional Test Development into a CAD Entvironment for VLSI; Proc. ICCD, Port Chester, NY, USA, 1988
  152. Alfs, G., Hartenstein, R., Riedmueller, M., Wodtko, A.:Integration of Simulation, Test Development and Test in a High Level Design Environment; in: (ed.: D. Edwards) Proceedings IFIP - TC-10 Conference on Design Methodologies for VLSI and  Computer Architecture, Pisa, Italy, Sept. 19 - 21, 1988, North Holland 1988
  153. Hartenstein, R., Ryba, M.: Computer Structure Partitioning Schmemes; in: (ed.: D. Edwards) Proceedings IFIP - TC-10 Conference on Design Methodologies for VLSI and Computer Architecture, Pisa, Italy, Sept. 19 - 21, 1988, North Holland, Amsterdam, 1988
  154. Alfs, G., Hartenstein, R., Wodtko, A.: Integration of Test Development into the Design of Full Custom Circuits; Tagungsband  zur ITG-Fachtagung "Mikroelektronik fuer die Informationstechnik", Oct 3 - 5, 1988, Berlin, Germany. VDE-Verlag, Duesseldorf, 1988
  155. Jansen, K.: Transformations of RT descriptions guided by features of logic implementations to be verified; Proc. 2nd ABAKUS  workshop, Innsbruck, Austria, Sept. 1988
  156. Hartenstein, R., Lemmert, K.: A systolic design system using KARL; Proc. 2nd ABAKUS workshop, Innsbruck, Austria, Sept. 1988
  157. Hartenstein, R., Joerg, K., Welters, U.: A multiple abstraction level editor for VLSI design; Proc. 2nd ABAKUS workshop,  Innsbruck, Austria, Sept. 1988
  158. Hartenstein, R., Hauck, R., Lemmert, K.: Some new features in KARL-4 and superKARL - a survey ; Proc. 2nd ABAKUS workshop, Innsbruck, Austria, Sept. 1988
  159. Hauck, R.: KARL-4 - A hardware description language for the design and synthesis of digital hardware; Proc. 2nd ABAKUS  workshop, Innsbruck, Austria, Sept. 1988
  160. Alfs, G., Hartenstein, R., Riedmueller, M.: SCIL-III - A language for simulator and tester activation; Proc. 2nd ABAKUS workshop, Innsbruck, Austria, Sept. 1988
  161. Alfs, G., Hartenstein, R., Wodtko, A.: The KARATE system - Integrating functional test development into the KARL design  environment; Proc. 2nd ABAKUS workshop, Innsbruck, Austria, Sept. 1988
  162. Mayer, Th.: RANGECOUNTER - a Full Custom #circuit for the MoM; Projektarbeit, University of Kaiserslautern 1988
  163. Benzschawal, S.*: RTCLIB, A Library manager for  RTcode; Projektarbeit, University of Kaiserslautern 1988
  164. Schmidt, K.: NMOS Implementation of PATIL Arrays; Projektarb., University of Kaiserslautern 1988
  165. Mueller, R.*: MULTISHIFT - eine Vollkundenschaltung fuer die MoM: Layout und Simulation; Projektarbeit, University of Kaiserslautern 1988
  166. Nicklaus, H.: MULTISHIFT - a fullcustom circuit for the MoM: Spezifikation und Problemanalyse; Projektarbeit, University of Kaiserslautern 1988
  167. Ast, A.*: NMOS LSI Design of an Image Processor accepting Video Signals; Projektarbeit, University of Kaiserslautern 1988
  168. Duhl, M.*: Parametrischer Entwurf digitaler Schaltungen unter Verwendung der Sprache superKARL; Diplomarbeit, University of Kaiserslautern 1988
  169. Finkler D.*: PICT Generator for the MLED System; Projektarb., Univ.Kaiserslautern 1988
  170. Joerg K.: PTI - Implementation of a Procedural Tool Interface f.the MLED System; Diplomarbeit, University of Kaiserslautern 1988
  171. N. N.: SuperKARL Language User Manual; University of Kaiserslautern, 1988
  172. Bonomo, A., Italiano, M., Lavagno, L, Maggiulli, M. L., Melgara, M., Paolini, M., Stamelos, I.: BACH (Behavioural-Level Automated Compilation of Hardware): An Integrated ASIC Synthesis System; ESPRIT Technical Week, Brussels, Belgium 1988
  173. R. Hartenstein, K. Lemmert: SYS3: A CHDL-based Systolic Synthesis System; s.[176]
  174. K. Lemmert: SYS3 Systolic Synthesis System around KARL,  Ph. D. dissertation, University of Kaiserslautern, 1989
  175. A. Wodtko: On The Automatic Generation Of Test Patterns From Mixed-Level Hardware Descriptions, Ph. D. dissertation,  University of Kaiserslautern, 1989
  176. J. Darringer, F. J. Rammig: Computer Hardware Description Languages and their Applications; North Holland, Amsterdam, 1990
  177. R. Hauck: On Generic Hardware Descriptions; Dissertation, University of Kaiserslautern, 1992
  178. R. Hartenstein: The History of KARL and ABL; s.[179]
  179. J. Mermet: Fundamentals and Standards in Hardware Description Languages; ISBN 0-7923-2513-4, Kluwer Academic  Publishers, September 1993.
 
Contents of this page List of other pages
KARL Licensee Sites
Early textual KARL-II implementation package
KARL language versions
Software interfaced to KARL, ABLED and RTcode
  (the KARL intermediate form)
Other KARL related software or KARL Dialects
Studies including KARL
Major designs implemented in using KARL and ABLED
KARL-related Quotation Index

KARL-related Literature

The nomination procedure:
Nomination Calendar
filled out B-27 Form from Prof Baier
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About the candidate:
Bio and History of E.I.S.
Technical Presentations
Papers and Books
Theses directed
Advisory Activities
Serving Conferences and Journals
Serving Professional Organizations

KARL users
History of KARL
filled out B-27 Form from Prof Baier