Call for Papers
5th Reconfigurable Architectures Workshop (RAW'98)
March 30, 1998, Orlando, Florida, USA
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This workshop is the 5th one in a series held at Cancun, Mexico (1994),
Santa Barbara, California (1995), Honolulu, Hawaii (1996) and Geneva, Switzerland
(1997).
RAW-98 is part of the first merged Symposium IPPS/SPDP 1998, being
held
at Delta Orlando Ressort, Orlando, Florida, USA. RAW-98 will be held at March 30, the first day of IPPS/SPDP-98. RAW-98 is one of the 12 specialized workshops held at the first or last day of IPPS/SPDP-98.
Goals and Visions of the Workshop
The recent decade has witnessed enormous technological advances, a
deeper appreciation of the power of the use of reconfigurable technology
platforms, and a better understanding of computing in time and in space.
The methodology of reconfigurable circuits and systems is evolving from
tinkertoy approach to an:
The building of reconfigurable systems can only be achieved by building on the experience in different areas, and close interaction between them to identify and solve the remaining problems. The primary objective of this workshop is to provide opportunity for creative interaction between researchers actively involved in the fabrication, design, applications and enabling technologies of reconfigurable architectures.
Scope of the Workshop
The workshop will feature several sessions of submitted paper presentations
and proceedings will be available at the symposium and by public ftp. Authors
are invited to submit manuscripts which demonstrate original and on-going
research in areas of Reconfigurable Architectures, implementations, algorithms
and applications. The topics of interest include, but are not limited to:
Reconfigurable Systems
- Reconfiguration Models
- Implementations
- Systems Complexity
- Scalable Programmable Logic
- Architectures
- Technology
- CAD tools
- Applications
- Evolvable and Adaptable Systems
- Reconfigurable Custom Computing Machines
- Reconfigurable Accelerators and their Applications
- Problem Solving Paradigms
- Image Processing
- Geographic Information Systems
- Graphics and Animation
- Algorithms (arithmetic/geometric/graph/numerical/randomised)
- Industrial applications and experiences
- Software to Hardware Migration for Speed-up
- Run Time to Compile Time Migration for Speed-up
- Hardware/Software Co-Design using reconfigurable devices
- Profiling and Hardware / Software Partitioning
- New Paradigms and Basic Research Aspects
- High-level Development Support
- Reconfiguration from Programming Language Sources
- Innovative Compilation Techniques
- Adapting Parallelizing Compilation Techniques for Structural Programming
- Benchmarks for Reconfigurable Hardware
- introducing structural programming in CS curricula
- introducing reconfigurable architectures and technology platforms in CS&E curricula
- lab courses integrating structural and procedural programming
- educational experiences on reconfigurable systems
- experiences in hardware / software co-education
We are witnessing the beginning of a paradigm change. Hardware has become soft. A second world of programming joins the traditional procedural programming: the world of structural programming. In the long term this will revolutionize the entire computing science. The mainly procedurally oriented traditional computing science will end up in a duality of computing in time and computing in space. The crystalization point of this overlap is already here. It is the area of systolic array synthesis, where time and space appear within the same formula, and, which provides first mappings between both worlds. (Systolic arrays stress computing in space, because the locality of an operation in a particular PE is a central concept. In classical parallel computing (except SIMD and similar) locality is not interesting, since processors have addresses.)
This is just the beginning. You are encouraged to submit your cool ideas, your hot implementations, and your exciting visions - to accelerate this march to new horizons.
Bridging the Gap
Until recently the populations of the R&D scene of parallel computing
or high performance computing on one side, and the scenes dealing with
reconfigurable hardware platforms have been non-overlapping. But both populations
have the same goal: high performance by parallelism. Until recently calls
for papers and participants on reconfigurable platforms, systems, and applications
attracted only hardware experts. Most of them practice hardware / software
co-design: linking structurally programmed accelerator hardware to traditional
software running on a procedurally programmed host system. But high performance
people, supercomputing people, parallel computing people, etc. went only
to their own conferences. Until recently only a few of them had heard anything
about FPGAs and other reconfigurable platforms and how to use them for
speed-up. The time has come to bridge that gap: we need your help.
Program Committee (confirmation pending)
- Peter Athanas, Virginia Tech (USA) <athanas@pequod.ee.vt.edu>
- Don Bouldin, University of Tennessee (USA) <bouldin@microsys6.engr.utk.edu>
- Klaus Buchenrieder, Siemens Research (D) <Klaus.Buchenrieder@mchp.siemens.de>
- Steven Casselman, Virtual Computer Corp. (USA) <sc@vcc.com>
- Pak Chan, University of California Santa Cruz (USA) <pak@cse.usc.edu>
- Bernard Courtois, Univ. Grenoble (F) <Bernard.Courtois@imag.fr >
- Hossam Elgindy, Univ. of Newcastle (AUS) <hossam@cs.newcastle.edu.au >
- Rolf Ernst, Univ. Braunschweig (D) <ernst@ida.ing.tu-bs.de>
- Masahiro Fujita, Fujitsu Labs. (USA) <fujita@fla.fujitsu.com>
- Manfred Glesner , TH Darmstadt (D) <glesner@mes.th-darmstadt.de>
- John Gray, Xilinx Corp. (UK) <john.gray@xilinx.com>
- Reiner Hartenstein, Univ. Kaiserslautern (D) <hartenst@rhrk.uni-kl.de>
- Mark Jones, Virginia Tech (USA) <mtj@vt.edu>
- John McHenry, National Security Agency (USA) <jtmchen@afterlife.ncsc.mil>
- Brent Nelson, Brigham Young Univ. (USA) <nelson@ee.byu.edu>
- Viktor Prasanna, Univ. of Southern California (USA) <prasanna@ganges.usc.edu>
- Hartmut Schmeck, Univ. Karlsruhe (D) <schmeck@aifb.uni-karlsruhe.de>
- Herman Schmitt, Carnegie Mellon Univ. (USA) <herman@ece.cmu.edu>
- Michal Servit, Techn. Univ. Prague (CR) <servit@cslab.felk.cvut.cz>
- Takayuki Yanagawa, NEC, Tokyo (JP) <yanagawa@octs.ho.nec.co.jp>
- Hiroto Yasuura, Kyushu University (JP) <yasuura@c.csce.kyushu-u.ac.jp>
All papers will be reviewed. Electronic submissions (in postscript format) are encouraged and should be sent to
hartenst@rhrk.uni-kl.de and
abakus@informatik.uni-kl.de (please, use both, simultaneously)
The workshop proceedings will be published by a professional publisher, taking care of ISBN number and Library of Congress catalog number.
Important Dates:
- Manuscripts due November 15, 1997.
Notification of review decisions December 19, 1997.
Final version due January 23, 1998.
please contact any of the workshop co-chairs:
- Reiner W. Hartenstein
- Universitaet Kaiserslautern (Germany)
- E-mail: hartenst@rhrk.uni-kl.de
- and abakus@informatik.uni-kl.de (please, use both, simultaneously),
- FAX: +49 631 205 2640
- and +49 7251 14823 (please, use both, simultaneously)
- Peter M. Athanas
Virginia Polytechnic Institute and State University
The Bradley Dept. of Electr. and Comp. Eng.
Blacksburg, VA 24061-0111
E-mail: athanas@vt.edu
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