PATMOS 2000     International Workshop - Power and Timing Modeling, Optimization and Simulation 
Göttingen, Germany - September 13-15, 2000    --    http://patmos2000.uni-hannover.de 
     
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Workshop Program 


Advance Program (PDF)  Advance Program (PDF for duplex printers) 

Schedule

Time
Wednesday, 
Sept. 13
Thursday, 
Sept. 14
Friday, 
Sept. 15
8:00-9:15 Registration  
9:00-10:30 (9:15)     Opening System-Level Design
Design of Multimedia Processing Applications
10:30-11:00
Coffee Break
11:00-12:30
RTL Power Modeling
Transistor-Level Modeling
Adiabatic Design and Arithmetic Modules
12:30-14:00
Lunch Break
14:00-15:30
Power Estimation and Optimization
Asynchronous Circuit Design
Analog-Digital Circuits Modeling
15:30-16:00
Break
 
 
 16:00-19:00
Guided Tour to Göttingen
 16:00-17:30
Power Efficient Technologies
 16:00
Workshop End
 
 19:00-21:00
Welcome Buffet
 19:30-22:30
Banquet
 
     
       

Sessions

Session 1

Opening
1.1 Welcome
P. Pirsch, University of Hannover, Germany
1.2 The PATMOS2000 Program
D. Soudris, Democritus University of Thrace, Greece
1.3 Constraints, Hurdles, and Opportunities for a Successful European Take-Up Action
R. van Leuken, R. Nouta, A. de Graf, Delft University of Technology, The Netherlands
 

Session 2

RTL Power Modeling
2.1 Architectural Design Space Exploration Achieved through Innovative RTL Power Estimation Techniques
M. Anton, M. Chinosi, D. Sirtori, R. Zafalon, STMicroelectronics, Italy
2.2 Power Models for Semi-autonomous RTL Macros
A. Bogliolo, University of Ferrara, Italy
E. Macii, V. Mihailovici, M. Poncino, Polytechnical University of Torino, Italy
2.3 Power Macro-Modelling for Firm-Macros
G. Jochens, L. Kruse, E. Schmidt, A. Stammermann, W. Nebel, OFFIS Research Institute, Germany
2.4 RTL Estimation of Steering Logic Power
C. Anton, P. Civera, I. Colonescu, E. Macii, M. Poncino, Polytechnical University of Torino, Italy
A. Bogliolo, University of Ferrara, Italy
 

Session 3

Power Estimation and Optimization
3.1 Reducing Power Consumption through Dynamic Frequency Scaling for a Class of Digital Receivers
N. D. Zervas, S. Theoharis, A. P. Kakaroudas, G. Theodoridis, C. E. Goutis, University of Patras, Greece
D. Soudris, Democritos University of Thrace, Greece
3.2 Framework for High-Level Power Estimation of Signal Processing Architectures
A. Freimann, University of Hannover, Germany
3.3 Adaptive Bus Encoding Techique for Switching Activity Reduced Data Transfer over Wide System Busses
C. Kretzschmar, R. Siegmund, D. Müller, Chemnitz University of Technology, Germany
3.4 Accurate Power Estimation of Logic Structures Based on Timed Boolean Functions
G. Theodoridis, S. Theoharis, N. D. Zervas, C. E. Goutis, University of Patras, Greece
 

Session 4

System-Level Design
4.1 A Holistic Approach to System Level Energy Optimization
M. J. Irwin, M. Kandemir, N. Vijaykrishnan, A. Sivasubramaniam, The Pennsylvania State University, USA
4.2 Early Power Estimation for System-on-Chip Designs
M. Lajolo, NEC C&C Research Labs, Princeton, USA
L. Lavagno, University of Udine, Italy
M. Sonza Reorda, M. Violante, Polytechnical University of Torino, Italy
4.3 Design-Space Exploration of Low Power Coarse Grained Reconfigurable Datapath Array Architectures
R. Hartenstein, Th. Hoffmann, U. Nageldinger, University of Kaiserslautern, Germany
 

Session 5

Transistor-Level Modeling
5.1 Internal Power Dissipation Modeling and Minimization for Submicronic CMOS Design
P. Maurine, M. Rezzoug, D. Auvergne, University of Montpellier, France
5.2 Impact of Voltage Scaling on Glitch Power Consumption
H. Eriksson, P. Larsson-Edefors, University of Linköping, Sweden
5.3 Degradation Delay Model Extension to CMOS Gates
J. Juan-Chico, M. J. Bellido, P. Ruiz-de-Clavijo, A. J. Acosta, M. Valencia, Centro Nacional de Microelectrónica, Spain
5.4 Second Generation Delay Model for Submicron CMOS Process
M. Rezzoug, P. Maurine, D. Auvergne, University of Montpellier, France
 

Session 6

Asynchronous Circuit Design
6.1 Semi-modular Latch Chains for Asynchronous Circuit Design
N. Starodoubtsev, A. Bystrov, A. Yakovlev, University of Newcastle upon Tyne, UK
6.2 Asynchronous First-In First-Out Queues
F. Pessolano, South Bank University, London, UK
J. WL Kessels, Philips Research Laboratories, Eindhoven, The Netherlands
6.3 Comparative Study on Self-Checking Carry-Propagate Adders in Terms of Area, Power and Performance
A. P. Kakaroudas, K. Papadomanolakis, V. Kokkinos, C. E. Goutis, University of Patras, Greece
6.4 VLSI Implementation of a Low-Power High-Speed Self-Timed Adder
P. Corsonello, S. Perri, G. Cocorullo, University of Calabria, Italy
 

Session 7

Power Efficient Technologies
7.1 Low Power Design Techniques for Contactless Chipcards
H. Sedlak, Infineon Technologies, Munich, Germany
7.2 Dynamic Memory Design for Low Data-Retention Power
J. Kim, M. C. Papaefthymiou, University of Michigan, USA
7.3 Double-Latch Clocking Scheme for Low-Power I.P. Cores
C. Arm, J.-M. Masgonty, C. Piguet, CSEM, Switzerland
 

Session 8

Design of Multimedia Processing Applications
8.1 Architecture, Design, and Verification of an 18 Million Transistor Digital Television and Media Processor Chip
S. Dutta, Philips Semiconductors, Sunnyvale, USA
8.2 Cost-efficient C-Level Design of an MPEG-4 Video Decoder
K. Denolf, P. Vos, J. Bormans, I. Bolsens, IMEC, Belgium
8.3 Data-Reuse and Parallel Embedded Architectures for Low-Power, Real-Time Multimedia Applications
D. Soudris, A. Argyriou, M. Dasygenis, K. Tatas, A. Thanailakis, Democritus University of Thrace, Greece
N. D. Zervas, C. E. Goutis, University of Patras, Greece
 

Session 9

Adiabatic Design and Arithmetic Modules
9.1 Design of Reversible Logic Circuits by Means of Control Gates
A. De Vos, B. Desoete, University of Gent, Belgium
A. Adamski, P. Pietrzak, M. Sibinski, T. Widerski, Poliytechnical University of Lodz, Poland
9.2 Modeling of Power Consumption of Adiabatic Gates versus Fan In and Comparison with Conventional Gates
M. Alioto, G. Palumbo, University of Catania, Italy
9.3 An Adiabatic Multiplier
C. Saas, A. Schlaffer, J. A. Nossek, Technical University of Munich, Germany
9.4 Logarithmic Number System for Low-Power Arithmetic
V. Paliouras, T. Stouraitis, University of Patras, Greece
 

Session 10

Analog-Digital Circuits Modeling
10.1 An Application of Self-timed Circuits to the Reduction of Switching Noise in Analog-Digital Circuits
R. Jiménez, A. J. Acosta, E. J. Peralías, A. Rueda, Centro Nacional de Microelectrónica, Spain
10.2 PARCOURS - Substrate Crosstalk Analysis for Complex Mixed-Signal-Circuits
A. Hermann, E. Barke, University of Hannover, Germany
M. Silvant, Simplex Solutions, Voiron, France
J. Schlöffel, Philips Semiconductors, Hamburg, Germany
10.3 Influence of Clocking Strategies on the Design of Low Switching-Noise Digital and Mixed-Signal VLSI Circuits
A.J. Acosta, R. Jiménez, J. Juan, M.J. Bellido, M. Valencia, Centro Nacional de Microelectrónica / University of Sevilla, Spain
10.4 Computer Aided Generation of Analytic Models for Nonlinear Function Blocks
T. Wichmann, University of Kaiserslautern, Germany
M. Thole, Infineon Technologies, Munich, Germany
 
A. Freimann, 13.7.2000