1st Call for papers
March 25, 2002
workshop is the twelfth in a series of international workshops having been
held in several places in Europe (visit the web site http://www.patmos-conf.org).
PATMOS has over the years evolved into a well established and outstanding
series of open European events on power and timing aspects of integrated
circuit design. The increased interest, especially in low-power design,
adds further momentum to the interest in this workshop. Despite its growth,
the workshop can still be considered as an informal but very focused conference,
featuring high-level scientific presentations together with open discussions
and panel sessions in a free and easy environment. In the year 2002, the
venue will be in Sevilla, Spain, organized by the Microelectronics Spanish
Center (IMSE-CNM) and the University of Seville. Seville is the major city
in the south-west of Spain and one of its richest historic, cultural and
objective of this workshop is to provide a forum to discuss and investigate
the emerging problems in the design methodologies and CAD-tools for the
new generation of IC technologies. A major emphasis of the technical program
is on speed and low-power aspects with particular regard to modeling, characterization,
design, and architectures. The scope of the workshop includes, but is not
limited to design and CAD aspects of:
are invited for regular presentations and discussion sessions. Prospective
authors for regular presentations are invited to submit their complete
paper including a 100-word abstract and illustrations in A4 camera ready
format, not exceeding 10 pages. Electronic submission is required and should
follow the style for the final publication. Check the web-page http://www.patmos2002.org
for complete author and submission instructions. Submitted papers will
be reviewed formally and anonymously by several reviewers.
power design: high performance low power systems, ultra low power systems,
and synthesis: timing, power, low-voltage, interconnect, crosstalk.
design: clocking, synchronization, asynchronous and self timed systems,
low voltage low power logic families, logic parallelization, pipelining,
fast low power arithmetic.
design: module generation, library optimization and characterization,
test and characterization: low VT low voltage process, SOI, IDDQ, models
and parameter extraction, experimental design for process control.
methods and CAD tools: for low voltage low power design, high speed
between devices, architectures and technologies, benchmark comparison.
for the panel sessions and special sessions are encouraged and must be
received also not later than March 25, 2002.
for submission of a paper:
for submission of final paper: