Thursday September 22

 

08:30 – 09:30 Keynote

Session chair: D. Verkest, IMEC, Belgium

Various Low Power Techniques and Solutions

Gunok Jong

Samsung, Korea.

 

09:30– 11:10 Session 5:  Low-power circuits

Session chair: N. Azemard, LIRRM, France

An Activity Monitor for Power/Performance Tuning of CMOS Digital Circuits.

Josep Rius1, José Pineda2 and Maurice Meijer2.

1 Universitat Politčcnica de Catalunya, Spain.

2 Philips Research Laboratories, Eindhoven, The Netherlands.

Power Management for Low-Power Battery Operated Portable Systems Using Current-Mode Techniques

Jean-Félix Perotto, Stefan Cserveny.

CSEM SA, Neuchâtel, Switzerland.

Power consumption in reversible logic addressed by a ramp voltage

Alexis De Vos and Yvan Van Rentergem.

Imec VZW. and Universiteit Gent, Belgium.

Leakage and Dynamic Glitch Power Minimization Using Integer Linear Programming for Vth Assignment and Path Balancing.

Yuanlin Lu and Vishwani D. Agrawal.

Auburn University, USA

Back Annotation in High Speed Asynchronous Design.

Pankaj Golani and Peter A. Beerel.

University of Southern California, Los Angeles, USA.

 

11:10 – 11:40 Coffee break & posters

 

11:40– 13:00 Session 6:  System-on-Chip Design

Session chair: R. Reis, UFRGS, Brazil

Optimization of Reliability and Power Consumption in Systems on a Chip.

T. Simunic1, K. Mihic2, G. De Micheli2

1 UCSD, CA, USA.

2 Stanford U., CA, USA.

Performance Gains from Partitioning Embedded Applications in Processor-FPGA SoCs.

Michalis D. Galanis, Gregory Dimitroulakos, Costas E. Goutis.

University of Patras, Greece.

A Thermal Aware Floorplanning Algorithm Supporting Voltage Island for Low Power SOC Design

Yici Cai, Bin Liu, Qiang Zhou, Xianlong Hong

Tsinghua University, P.R. China.

Power Supply Selective Mapping for Accurate Timing Analysis

Mariagrazia Graziano1, Cristiano Forzan2, and Davide Pandini2

1 Politecnico di Torino, Italy.

2 STMicroelectronics, Agrate Brianza, Italy.

 

13:00 – 14:10 Lunch

 

14:10– 15:50 Session 7:  Busses and Interconnections

Session chair: J. Jorge, IMSE-CNM, Spain

Switching Sensitive Driver Circuit to Combat Dynamic Delay in On-Chip Buses

Roshan Weerasekera1, Li-Rong Zheng1, Dinesh Pamunuwa2 and Hannu Tenhunen1

1 KTH Microelectronics and Information Technology, Kista, Sweden.

2 Lancaster University, United Kingdom.

PSK Signalling on NoC Buses.

Crescenzo D'Alessandro, Delong Shang, Alex Bystrov, Alex Yakovlev

University of Newcastle upon Tyne, United Kingdom.

Exploiting Cross-Channel Correlation for Energy-Efficient LCD Bus Encoding.

Ashutosh Chakraborty, Enrico Macii, Massimo Poncino.

Politecnico di Torino, Torino, Italy.

Closed-Form Bounds for Interconnect-Aware Minimum-Delay Gate Sizing

Giorgos Dimitrakopoulos and Dimitris Nikolos.

University of Patras, Greece.

Efficient Simulation of Power/Ground Networks with Package and Vias.

Jin Shi1, Yici Cai1, Xianlong Hong1, Shelton X-D Tan2.

1 Tsinghua University, Beijing, P.R.China

2 University of California at Riverside, USA.

 

15:50 – 16:20 Coffee break & posters

 

16:20– 17:40 Session 8:  Modeling

Session chair: C. Piguet, CSEM, Switzerland

Output Resistance Scaling Model for Deep-Submicron CMOS Buffers for Timing Performance Optimisation.

Gregorio Cappuccino, Andrea Pugliese, Giuseppe Cocorullo.

University of Calabria, Rende, Italy.

Application of Internode model to global power consumption estimation in SCMOS gates

A. Millan, M. J. Bellido, J. Juan, P. Ruiz-de-Clavijo, D. Guerrero, E. Ostua and J. Viejo

Centro Nacional de Microelectronica, Sevilla, Spain.

Compact Static Power Model of Complex CMOS Gates

Jose L Rosselló, Sebastiŕ Bota and Jaume Segura.

Universitat de les Illes Balears, Palma de Mallorca, Spain.

Statistical Critical Path Analysis Considering Correlations

Yaping Zhan1, Andrzej J. Strojwas1, Mahesh Sharma2, David Newmark2

1 Carnegie Mellon University, Pittsburgh, PA, USA

2 Advanced Micro Devices Inc., Austin, TX, USA

 

17:40 – Invited talk

Session chair: V. Paliouras, University of Patras, Greece

Cryptography: Circuits and Systems Approach

O. Koufopavlou, G. Selimis, N. Sklavos, P. Kitsos.

University of Patras, Greece

 

Posters:  Digital Circuits

Area-Aware Pipeline Gating for Embedded Processors

Babak Salamat and Amirali Baniasadi.

University of Victoria, Canada.

Fast Low-Power 64-bit Modular Hybrid Adder

Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo.

University of Calabria, Italy.

Speed Indicators for Circuit Optimization

A. Verle,  A. Landrault, P. Maurine, N. Azémard.

LIRMM, Université de Montpellier, France.

Synthesis of Hybrid CBL/CMOS Cell using Multi-objective Evolutionary Algorithms

Francisco de Toro1, Raul Jimenez2, Manuel Sanchez2, and Julio Ortega2

1 Universidad de Granada, Spain.

2 Universidad de Huelva, Spain.

Power-Clock Gating in Adiabatic Logic Circuits

Philip Teichmann1, Jürgen Fischer1, Stephan Henzler1, Ettore Amirante2,

Doris Schmitt-Landsiedel1.

1 Technical University Munich, Germany.

The design of an asynchronous carry-lookahead adder based on data characteristics

Yijun Liu, Steve Furber.

University of Manchester, UK.

Efficient Clock Distribution Scheme for VLSI RNS Enabled Controllers

Daniel González, Luis Parrilla, Antonio García, Encarnación Castillo, Antonio Lloris

University of Granada, Spain.

Power Dissipation Impact of the Technology Mapping Synthesis on Look-up Table Architectures 

Francisco-Javier Veredas1 2, Jordi Carrabina3

1 Infineon Technologies AG, Munich, Germany.

2 University of Ulm, Germany.

3 University Autonoma of Barcelona, Spain.