Friday, October 6, 95


Invited Paper

9h00 - 9h45
Chair: C. Piguet

Simulation Algorithms, Power Estimation and Diagnostics in PowerMill
Dr. Jacques Benkoski, EurEPIC, Grenoble, France


Coffee Break

9h45 - 10h00


Session 8: Low-Power Design and Reliability

10h00 - 11h00
Chair: J. Figueras, Univ. of Catalunya, Spain

S8.1 Low-Power Low-Voltage EEPROM Designed for Operation down to 1.2 Volt
N. Jeannet, EM-Microelectronic Marin, Switzerland

S8.2 Reliability and Self-Repair of Integrated Circuits
C. Piguet, P. Weiss, P. Marchal, CSEM, Neuchtel, Switzerland


Short Break

11h00 - 11h15


Session 9: CAD Tools for Low-Power

11h15 - 12h45
Chair: M. Robert, LIRMM, France

S9.1 A New Method for Performance Oriented Logic Extraction
H. Vaishnav, M. Pedram, UCLA, Los Angeles, USA

S9.2 PAPSAS: A Fast Switching Activity Simulator
P. H. Schneider, Siemens AG Munich, Univ. of Munich, Germany

S9.3 Delay Analysis and Critical Path Search in the TIME Tool for VLSI CMOS
L. F. Uebel, S. Bampi, Informatics Institute, Porto Alegre, Brasil


Closing Session

12h45-13h00
Chair: Wolfgang Nebel, Christian Piguet


Lunch

13h00 - 14h00


Workshop Closure


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