Thursday, October 5, 95


Invited Paper

9h00 - 9h45
Chair: W. Nebel

A Comparison Study of Switching Activity Estimation Techniques
Prof. Dr. Massoud Pedram, Chih-shun Ding, UCLA, Los Angeles, USA


Coffee Break

9h45 - 10h15


Session 5 : Glitch and Short-Circuit Power Dissipation Modeling

10h15 - 12h30
Chair: D. Auvergne, LIRMM, France

S5.1 Glitch Power Dissipation Model
C. Metra, M. Favalli, B. Ricco, Univ. of Bologna, Italy

S5.2 Dynamic Gate Delay Modeling for Accurate Estimation of Glitch Power at Logic Level
M. Eisele, Univ. of Munich, J. Berthold, Siemens AG, Munich, Germany

S5.3 The Effect of Glitches on CMOS Buffer Optimization
M. Favalli, C. Metra, Univ. of Bologna, Italy

S5.4 Short-Circuit Power Dissipation Calculation on CMOS Inverters Using the Equivalent Short-Circuit Capacitance Concept
S. Turgis, N. Azemard, D. Auvergne, LIRMM, Montpellier, France


Lunch

12h30 - 14h00


Session 6: Low-Power Multipliers

14h00 - 15h30
Chair: A. Guyot, TIMA/INPG, Grenoble, France

S6.1 Low-Power Array Multipliers with Transition-Retaining Barriers
E. Mussol, J. Cortadella, Univ. of Catalunya, Spain

S6.2 Impact of Adding Schemes on Switching Activity of Digital Multipliers
V. Moshnyaga, K. Tamaru, Univ. of Kyoto, Japan

S6.3 On the Usefulness of Pipelining and Wave Pipelining as Low-Power Design Technique
E. I. Boemo, S. Lopez-Buedo, J. Jauregui, G. Gonzales de Rivera, J. M. Meneses, Univ. of Madrid, Spain


Coffee Break

15h30 - 16h00


Session 7: Parasitic Coupling and Interconnections

16h00 - 17h30
Chair: S. R. Jones, Univ. of Loughborough, UK

S7.1 LAYIN: LAYout INspection CAD Tool Dedicated to the Parasitic Coupling Effects through the Substrate of Integrated Circuits
F. Clement, E. Zysman, M. Kayal, M. Declercq, EPFL, Lausanne, Switzerland

S7.2 Power Consumption due to the Capacitive Coupling of the Interconnection Wires in CMOS
M. A. Ortega, J. Figueras, Univ. of Catalunya, Spain

S7.3 On-Chip Measurements: A Way for Accurate Modeling of Interconnect Capacitances in CMOS Process
P. Nouet, A. Toulouse, LIRMM, Montpellier, France


Panel: Do You Need CAD Tools or Design Methods for Low-Power?

17h30 - 19h00
Moderator:
C. Piguet, CSEM, Switzerland

Panelists:

J. Benkoski, EurEPIC, France
M. Robert, LIRMM, France
M. Pedram, UCLA, USA


Banquet

20h00


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