Wednesday, October 4, 95


8h00 - 9h00

Opening Session (free admission)

9h00 - 9h30
Chair: Wolfgang Nebel, Christian Piguet

Welcome Address of the General Chair
Wolfgang Nebel

Welcome Address of the President of the Parliament of the State of Lower Saxony
Horst Milde

Introduction to the Program
Christian Piguet

Session 1: Self-Timed Design

9h30 - 10h30
Chair: H. Pfleiderer, Univ. of Ulm, Germany

S1.1 Design of Self-Timed Pipelined Architectures Using Petri Nets
O. Aumann, H.-J. Pfleiderer, Univ. of Ulm, Germany

S1.2 High-Level Design and Verification of an Asynchronous Queue Controller
P. G. Lucassen, J. T. Udding, Univ. of Groningen, The Netherlands

Coffee Break

10h30 - 11h00

Session 2: Delay Modeling

11h00 - 12h30
Chair: A. Rubio, Univ. de Catalunya, Spain

S2.1 Simultaneous Driver and Interconnection Sizing for Delay Optimization
D. Deschacht, C. Dabrin, LIRMM CNRS, Montpellier, France

S2.2 Investigation of CMOS Supply Voltage Scaling Limitations Using Accurate Delay Model
J. M. Daga, M. Robert, D. Auvergne, LIRMM, Montpellier, France

S2.3 Design and Sizing of Tapered Buffers for Minimum Power-Delay Product
S. Turgis, N. Azemard, D. Auvergne, LIRMM, Montpellier, France


12h30 - 14h00

Session 3: Adders and Algorithms Optimization

14h00 - 15h30
Chair: V. Moshnyaga, Univ. of Kyoto, Japan

S3.1 Timing Modeling for Adders Optimization
V. Tchoumatchenko, T. Vassileva, Univ. of Sofia, Bulgaria; A. Guyot, TIMA/INPG Grenoble, France

S3.2 A Comparison of Power Consumption in some CMOS Adder Circuits
D. J. Kinniment, B. Gao, Univ. of Newcastle upon Tyne, UK; J-D. Garside, Univ. of Manchester, UK

S3.3 Energy Consumption of Algorithms Realized in CMOS
J. Smit, Univ. of Twente, The Netherlands

Coffee Break

15h30 - 16h00

Session 4: Low-Power Logic Design

16h00 - 17h30
Chair: R. W. Hartenstein, Univ. of Kaiserslautern, Germany

S4.1 Technology Mapping with CMOS Parametrizable Gates
I. Urriza, J. Ignacio Garcia, D. Navarro, Univ. of Zaragoza, Spain

S4.2 Low-Voltage/Low-Power Parallelized Logic Modules
T. Schneider, V. von Kaenel, C. Piguet, CSEM, Neuchâtel, Switzerland

S4.3 Combinational CMOS Circuit Sizing and Layout Generation
J. Ignacio Garcia, D. Navarro, I. Urriza, Univ. of Zaragoza, Spain

Short Break

17h30 - 17h45

Panel: Does Deep Sub-Micron Imply a Return to Circuit Level Design?

17h45 - 19h00
W. Nebel, OFFIS, Germany


Franck Poirot, Compass Design Automation, France
Daniel Auvergne, LIRMM, France
Marc Laurent, MHS, France
Joan Figueras, UPC, Spain
Jose Luis Conesa Lareo, T I&D, Spain



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