sedes PATMOS'97 
Seventh International Workshop Program 
Université Catholique de Louvain 
Louvain-la-Neuve, Belgium
September 8-10, 1997 

11.3 Probability-Based Delay Analysis and Tuning of VLSI Circuits Using a Variance-Covariance Method ",Itiakorit J. Osele and Ramalingam Sridhar - Department of Electrical and Computer Engineering, The State University of New York at Buffalo, Buffalo, NY 14260

Abstract - A probability-based method is presented for the timing delay analysis and tuning of high performance VLSI circuits. The focus is on minimizing signal path skew, while using a set of wave-pipelined circuits as a vehicle of study. A recursive variance-covariance technique that assumes Gaussian delay distributions is used to i) balance, ii) quantify and iii) fine tune the critical path skew, and iv) calibrate performance. The results on the effectiveness of the technique to analyze and fine tune the wave-pipeline combinational circuits are reported.

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