Seventh International Workshop Program
ARAMIS A.S.B.L. - UCL-DICE
Université Catholique de Louvain
September 8-10, 1997
11.4 " Performance Analysis and Propagation Delay Time Estimation of Logic Families with HBTs ",J.del Pino, A.Hernández, J. García, B.González and A. Nunez - Centre for Applied Microelectronics. University of Las Palmas (Spain).
Abstract - A study of the operation
and performance of ECL and CML families implemented with HBTs has been
carried out. We have analyzed, by simulation, the behaviour of both logic
families and compared their performances with other high-speed FET based
families. As in silicon BJT-based circuits compared with CMOS, the HBT-based
families are faster but more power is consumed with regard to the other
FET families. We have also developed timing models expressed with simple
equations. These equations are technology dependent and predict the timing
operation of logic circuits as function of load capacitances and of fan-out.
It fits well the behaviour of the gates against HSPICE simulations with
errors smaller than 4% in all studied cases.
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