PATMOS'97  Seventh International Workshop Program  ARAMIS A.S.B.L. - UCL-DICE  Université Catholique de Louvain  Louvain-la-Neuve, Belgium September 8-10, 1997

12.1 " Cosimulation for ultra low power system ",J.P. Meunier, Steven Chau and Marty Rana, Synopsys PTG, USA.

ABSTRACT An innovative design methodology combining fast high level simulation with accurate transistor level simulation into a single integrated simulation environment is being presented. This methodology makes it possible to optimize a system on a chip by focusing on one section at a time simulated at the transistor level while the surrounding circuitry is simulated at high speed with a logic or behavioral simulator. The transistor level simulation allows an accurate power consumption simulation and an optimization of each section of the system for power and speed. The results obtained with an actual pacemaker circuit where power consumption is exceptionally critical are being presented.
jpm@epic.com