PATMOS'97  Seventh International Workshop Program  ARAMIS A.S.B.L. - UCL-DICE  Université Catholique de Louvain  Louvain-la-Neuve, Belgium September 8-10, 1997

12.2 " High Level Power Estimation ",Rafael Peset Llopis - Philips Research Laboratories Prof. Holstlaan 4, 5656 AA Eindhoven, The Netherlands

Abstract - High level power estimation is essential for designing complex low-power ICs. However, the lack of flexibility of all previously presented high level power estimation approaches limits their use to small (datapath) parts of ICs. In this paper a more general and flexible high level power estimation approach is presented, based on VHDL simulation. The obtained results are very encouraging.
peset@natlab.research.philips.com