sedes PATMOS'97 
Seventh International Workshop Program 
Université Catholique de Louvain 
Louvain-la-Neuve, Belgium
September 8-10, 1997 

2.1 Algorithms for Power Consumption Reduction and Speed Enhancement in High-Performance Parallel Multipliers ",Rafael Fried Swiss Federal Institute of Technology (EPFL), Electronics Laboratory, ELB-Ecuble ns, CH-1015 Lausanne, Switzerland

Abstract - This paper presents a new two-gate-delay implementation of the Booth encoder and partial product generator, which eliminates the unnecessary glitches associated with the Booth multiplier. In addition, a modified signed/unsigned (MSU) and modified sign-generate (MSG) algorithms, suitable especially for signed/unsigned multipliers, were developed in order to reduce the compression level needed in the Wallace tree, and hence reduce the multiplier hardware. Using these features reduces the multiplier array energy dissipation by about 35% and increases speed by about 10%.

Back to PATMOS '97 Program Home Page