sedes PATMOS'97 
Seventh International Workshop Program 
Université Catholique de Louvain 
Louvain-la-Neuve, Belgium
September 8-10, 1997 

2.2 Performance/Power Tradeoffs in ASIC Multipliers ",B.Laurent and G.Saucier, Institut National Polytechnique de Grenoble/CSI

This paper presents a wide array of efficient multipliers on an ASIC submicronic technology. Connection delays are taken into account through statistical wire lengthes. For power dissipation point of view, logic switching activity as well as glitching activity are both estimated. Firstly, the goal is to provide actual and accurate characterizations of classical multipliers. Secondly, most efficient architectures are compared such that optimized performance/power tradeoffs are derived.

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