sedes PATMOS'97 
Seventh International Workshop Program 
ARAMIS A.S.B.L. - UCL-DICE 
Université Catholique de Louvain 
Louvain-la-Neuve, Belgium
September 8-10, 1997 
PATMOS

2.4 Area/Time /Power Space Exploration in Module Selection for DSP High Level Synthesis ",S. Gailhard , O. Sentieys , N. Julien and E. Martin - IUP-LESTER - ENSSAT-LASTI

Abstract - Module selection is a basic architectural synthesis task that allows to optimise the cost of the dedicated circuits under real time constraint. Adding the power factor to the optimisation problem changes the working domain from two dimensions (Area/Time) to three dimensions (Area/Time/Power). However solving this problem by the best selection of the supply voltage and the operators set in a complex library remains unsolved. This paper presents an implementation of the module selection integrated in HLS GAUT tool and some results on a DWT algorithm.

Keywords - Module Selection, High Level Synthetics (HLS) for Low-Power, Area/Time/Power (ATP) Space Exploration, Real Time applications, Pipeline Architectures, Discrete Wavelet Transform (DWT).
gailhard@univ-ubs.fr


Back to PATMOS '97 Program Home Page
ATrullemans@dice.ucl.ac.be