sedes PATMOS'97 
Seventh International Workshop Program 
Université Catholique de Louvain 
Louvain-la-Neuve, Belgium
September 8-10, 1997 

3.2 Leakage power reduction for reactive computation ",Michele Favalli and Cecilia Metra - DEIS - University of Bologna Viale Risorgimento, 2 40136 Bologna, Italy

Abstract - Because of device scaling, leakage power is becoming a consistent fraction of the total power dissipated in CMOS circuits. In particular, it is dominant in reactive systems characterized by burst computations followed by long periods of inactivity. To reduce leakage power during such periods, we propose a new methodology that, differently from existing techniques, does not require process or electrical level modifications, but only the use of two additional power supplies.

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