sedes PATMOS'97 
Seventh International Workshop Program 
ARAMIS A.S.B.L. - UCL-DICE 
Université Catholique de Louvain 
Louvain-la-Neuve, Belgium
September 8-10, 1997 
PATMOS

4.2 Switch-Level Technology Mapping and Modeling ",Jordi Riera, Josep Velasco, Lluís Ribas, and Jordi Carrabina - Unitat de Microelectrònica - Dpt. Informàtica, Edifici C Universitat Autònoma de Barcelona

Abstract - As circuit specifications are growing in complexity, manual optimization methods for performance improvement become clearly insufficient, and should be replaced by automatic optimization CAD systems. In the logic synthesis field, performance restrictions have been traditionally taken into account by using a library of functions with many versions, each one of them having different performance trade-off. To attain good trade-off between the design parameters, big cell libraries are required. So, its development and maintenance costs are ever increasing. Our approach introduces performance-driven switch-level logic synthesis, closely tied to physical synthesis. This library-free approach, based on on-the-fly gate generation, allows using simplified performance models during logic synthesis. The final circuit performance is fine tuned by the conforming module generator.
riera@cnm.es


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