sedes PATMOS'97 
Seventh International Workshop Program 
Université Catholique de Louvain 
Louvain-la-Neuve, Belgium
September 8-10, 1997 

5.1 A New Method for Switching Activity Estimation of Logic Level Networks ",S. Theoharis, G. Theodoridis, D. Soudris and Goutis, VLSI Design Lab., University of Patras, Greece.

A new method for estimating the switching activity of combinational logic level networks is introduced. The proposed method has as inputs the signal probabilities of the primary inputs, the data correlation, and the after mapping structure of a logic network. Novel formulas for calculating the switching activity of basic gates are derived. Also, a new algorithm for propagating the signal probabilities through the logic network and calculating the switching activity is developped. The introduced method is accurate and fast. The accuracy stems from the fact that spacial, temporal, and structural correlations of the signals at all logic levels are taken into account. The small time cost is related with the reduced computational complexity in terms of multiplications. The experimental results show that the proposed method achieves significant reduction of the operations compared with the existing methods.

Back to PATMOS '97 Program Home Page