sedes PATMOS'97 
Seventh International Workshop Program 
Université Catholique de Louvain 
Louvain-la-Neuve, Belgium
September 8-10, 1997 

5.4 Application of Toggle-Based Power Estimation to Module Characterization ",Gerd Jochens, Lars Kruse and Wolfgang Nebel - OFFIS - Division 1 - Embedded Systems D - 26121 Oldenburg, Germany

Abstract This paper discusses the advantages and disadvantages of a fast methodology for power estimation of integrated CMOS circuits at gate level for RT-module power characterization. The methodology is based on a simple toggle count mechanism and embodied in our Toggle Power Simulator (TPS). TPS takes output loads and precharacterized gate internal power losses into account. The tool is integrated into the design kit of Atmel ES2 which itself is an add-on to the Cadence Design Framework II. Speed and accuracy of TPS are compared with HSpice simulations for RT level modules and ISCAS'85 benchmarks designed with a 1 µm standard cell library. The influence of several simulation parameters is revealed. Within an example it is demonstrated that errors, which are obtained in lower-level simulation, become visible in RT-level simulation results.

Back to PATMOS '97 Program Home Page