sedes PATMOS'97 
Seventh International Workshop Program 
Université Catholique de Louvain 
Louvain-la-Neuve, Belgium
September 8-10, 1997 

7.2 A New CMOS Ternary Logic Design for Low-power Low-voltage Circuits ",R. Mariani , F. Pessolano , and R. Saletti - Dip. di Ingegneria dell'Informazione University of Pisa Via Diotisalvi 2, I-56126 Pisa (Italy)

Abstract: This paper shows a new approach to low-power low-voltage CMOS Multiple-Valued (MVL) Ternary Logic, the ``complete model''. This logic uses standard technology processes and requires only an extra power supply more than binary CMOS circuits. Using an original characterisation of CMOS multivalued dynamic gates, it is shown as the advantages obtained are better noise margins and a lower power consumption as compared to other CMOS ternary solutions. As application of this approach, it is then discussed how general purpose asynchronous circuits can be designed with complete model ternary logic elements.

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