sedes PATMOS'97 
Seventh International Workshop Program 
ARAMIS A.S.B.L. - UCL-DICE 
Université Catholique de Louvain 
Louvain-la-Neuve, Belgium
September 8-10, 1997 
PATMOS

7.4 Area Reduction in Asynchronous Circuits by Signal Transition Graph Transformations ",George S. Panagiotaras and Odysseas Koufopavlou - VLSI Design Lab. Electrical & Computer Engineering Dpt. University of Patras, 26500 Patras, GREECE

ABSTRACT - Many asynchronous synthesis techniques utilize Signal Transition Graphs (STGs) as the initial circuit specification. In this paper, graph transformations that are applied to deterministic STGs are presented. Modifications of the graph concurrency achieve reduction in the resulting circuit area. The proposed transformations reduce the concurrency without influencing the functional operation of the circuit. The transformations are performed to a falling non-input signal transition. Three different STG examples are presented in the paper which indicate, by using the proposed transformations, up to 33 % reduction in the number of gates.
panagiot@ee.upatras.gr


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