sedes PATMOS'97 
Seventh International Workshop Program 
Université Catholique de Louvain 
Louvain-la-Neuve, Belgium
September 8-10, 1997 

8.2 Delay degradation effect in submicronic CMOS inverters ",J. Juan-Chico , M. J. Bellido , A. J. Acosta , A. Barriga , M. Valencia- Instituto de Microelectrónica de Sevilla. Centro Nacional de Microelectrónica. Edificio CICA, Avda. Reina Mercedes s/n, 41012-Sevilla, Spain.

Abstract - This communication presents the evidence of a degradation effect causing important reductions in the delay of a CMOS inverter when consecutive input transition are close in time. Complete understanding of the effect is demonstrated providing a quantifying model. Fully characterization as a function of design variables and external conditions is carried out, making the model suitable for using in library characterization as well as simulation at a transistor level. Comparison with HSPICE level 6 simulations shows satisfactory accuracy for timing evaluation.

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