sedes PATMOS'97 
Seventh International Workshop Program 
Université Catholique de Louvain 
Louvain-la-Neuve, Belgium
September 8-10, 1997 

8.4 Substrate Coupling Trends in Future CMOS Technologies ",Xavier Aragonès, José L. González, Antonio Rubio Departament d'Enginyeria Electrònica. UPC Gran Capità, S/N. Campus Nord. 08034 Barcelona

Abstract- Coupling through common silicon substrate has become an important limiting factor in high-performance mixed-signal ICs. A study of the evolution of this type of interaction with technology scaling down is presented in this paper. The level of noise when devices and parasitic elements are scaled down is obtained for a typical situation. High performance and low power scaling scenarios are considered, together with highly and lightly doped substrates. Previously, the best biasing strategies for each kind of substrate are determined. Results show that, as far as power-supply voltages are kept constant, noise will increase as devices are scaled down. When V dd is reduced, the amount of noise drops drastically, leading to an increase in signal-to-noise ratio for next-years technologies.

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