sedes PATMOS'97 
Seventh International Workshop Program 
Université Catholique de Louvain 
Louvain-la-Neuve, Belgium
September 8-10, 1997 

9.1 Glitch Current Peak Estimation in CMOS Gates ",Guoying Zuo, Nicholas Rumin Department of Electrical Engineering, Mcgill University 3480 University Street, Montreal, Quebec, H3A 2A7, Canada

Abstract - Neglecting the current due to voltage glitches in CMOS circuits can lead to large errors in the estimated power and ground bus currents. What little glitch-related research has been reported, has focused on glitch voltage analysis for power estimation. We present a model for the glitch current and time in a CMOS 2-input NOR gate. It is an empirical model which exploits the linear dependence of both quantities on the input signal overlap time. The model is accurate to within 15% of HSPICE with the level-3 MOSFET model. When used with a previously reported model for the analysis of currents due to complete logical transitions, the speed is two to three orders faster than HSPICE.

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