9.2 " Signal Transition Modeling in Submicronic CMOS Structures ", J-M. Daga and D. Auvergne, LIRMM - Université Montpellier, France.

Wave shape effects are of great importance in evaluating gate performances. Non zero signal rise and fall times contribute to gate propagation delays and must be considered for realistic characterization of standard cells. In this paper we present an accurate and simple method to model input rise and fall times. We show that this can be obtained in a framework of a more general macro model of delays, using step responses corrected for slow input ramp duration. The concept of fast and slow input transitions is clearly explained in terms of the drive current available in the structure. A first validation of this modeling has been obtained by comparing the calculated inverter output ramp duration to the simulated one (HSPICE level 6, 065 micron process). Finally both the delay and output ramp modeling are validated by comparing inverter array calculated and simulated total delay values.