sedes PATMOS'97 
Seventh International Workshop Program 
Université Catholique de Louvain 
Louvain-la-Neuve, Belgium
September 8-10, 1997 

9.3 On Estimating Leakage Power Consumption for Submicron CMOS Digital Circuits ",Antoni Ferre and Joan Figueras Departament d'Enginyeria Electronica Universitat Politecnica de Catalunya Diagonal 647, 08028 Barcelona

Abstract - The estimation of leakage power consumption of CMOS digital circuits taking into account the input/memory state and process variations is examined. Based on the sub-threshold leakage characterization at transistor and cell level, the leakage power consumption of a standard cell circuit is obtained. The dependence of this estimate on the channel lengths and their variation are used to find the variability of the leakage power consumption and its distribution under different statistical assumptions. The model predicts that the PLEAK power distribution is asymmetric around the nominal value in agreement with industrial experimental data [1]. A significant dependence of PLEAK on the input vector has been found. This dependence becomes stronger for circuits with shorter effective channel lengths. Finally, the problem of evaluating worst-case PLEAK has been addressed.

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