ARAMIS A.S.B.L. - UCL-DICE - Louvain-la-Neuve, Belgium

Université Catholique de Louvain

PATMOS'97

Seventh International Workshop Program

Louvain-la-Neuve, Belgium

September 8-10, 1997

During the conference, we will have the pleasure to present research cooperation programs supported by the European Commission, specially for the South countries, and Central Europe and new independant States . An industrial demo on the Mentor Graphics tool ELDO will also be organized during the breaks.

A visit the Comic Strip Museum of Brussels, a banquet in a charming area, and the variety and imagination of Louvain-la-Neuve, a young city for an old university, will certainly help in making the workshop more enjoyable.

DICE is the Microelectronic Laboratory of the Faculty of Applied Science at UCL, and deals with the design, fabrication and testing of integrated circuits. The design of ASICs in various application fields (image processing, biomedical ...) is one of its major activities, along with more fundamental areas: modelling of fabrication processes, design of novel devices, mixed and analog ICs, design methodologies ...

Prof. Dr. Anne-Marie Trullemans
UCL-DICE
Place du Levant, 3
B-1348 Louvain-la-Neuve, Belgium
phone: +32 (0) 10 47-2565
fax.: +32 (0) 10 47-2598
e-mail: ATrullemans@dice.ucl.ac.be

Program Chair:

Prof. Dr. Bruno Riccò
DEIS Universita di Bologna
V. le Risorgimento 2
I-40136 Bologna, Italy
phone: +39 (0) 51 644-3018
fax.: +39 (0) 51 644-3073
e-mail: bricco@deis.unibo.it

Conference Secretariat:

MMrs. Nathalie Braun and Caroline Cavenaile
ARAMIS asbl - c/o FPMs - Electronic Service
Boulevard Dolez, 31
B-7000 Mons, Belgium
phone: + 32 (0) 65 37 42 26
mobile phone: + 32 (0) 75 89 53 38
fax.: + 32 (0) 65 37 42 36
e-mail: aramis@muelec.fpms.ac.be

Steering Committee:

D. Auvergne, U. Montpellier, France
R. Hartenstein, U. Kaiserslautern, Germany
W. Nebel, U. Oldenburg, Germany
C. Piguet, CSEM, Switzerland
B. Riccò, U. Bologna, Italy
A. Rubio, U. Catalunya, Spain
A.-M. Trullemans, U. Louvain, Belgium

Program committee:

D. Auvergne, U. Montpellier , France
J. Benkoski, EurEPIC, France
M. Declercq, EPF-Lausanne, Switzerland
G. De Micheli, Stanford, USA
M. Favalli, U. Bologna, Italy
J. Figueras, U. Catalunya, Spain
A. Guyot, INPG Grenoble, France
R. Hartenstein, U. Kaiserslautern, Germany
S. Jones, U. Loughborough, U.K.
V. Moshnyaga, U. Kyoto, Japan
W. Nebel, U. Oldenburg, Germany
H. Nguyen, Bull Paris, France
A. Nunez, U. Las Palmas, Spain
M. Pedram, U. Southern California, USA
H. Pfleiderer, U. Ulm, Germany
C. Piguet, CSEM, Switzerland
R. Reis, U. Porto Alegre, Brazi
l B. Riccò, U. Bologna, Italy
M. Robert, U. Montpellier , France
A. Rubio, U. Catalunya, Spain
J. Sparsø, U. Lyngby, Denmark
A. Stempkowsky, U. Moscov, Russia
A. Strojwas, U. Carnegie Mellon, USA
C. Svensson, U. Linköping, Sweden
A.-M. Trullemans, U. Louvain, Belgium

Local Organizing Committee:

by ARAMIS, asbl , Belgium

Prof. R.G. Crappe, FPMs, Mons
Prof Ch. Trullemans, UCL, Louvain-la-Neuve
Prof J. Destiné, ULg, Liège
Prof. J.-L. Van Eck, ULB, Brussels

Welcome   A.-M. Trullemans

The PATMOS 1997 program   B. Riccò

1.1 Invited talk: "Modeling, Analysis and Optimization of Power Dissipation at the Instruction Level", Sharad Malik, University of Princeton, USA.

1.2 Invited talk: "Modeling and Simulation for Low Power in Mixed-signal Systems", G. Gielen, KUL-ESAT, Belgium.

Coffee break

11:00 - 12:30 SESSION 2: High-level Synthesis
  Chair: R. Hartenstein

2.1 "Algorithms for Power Consumption Reduction and Speed Enhancement in High-Performance Parallel Multipliers", Rafael Fried, EPFL - LEG-DE, Switzerland.

2.2 "Performance/Power Tradeoffs in ASIC Multipliers", B. Laurent and G. Saucier, INPG/CSI, France.

2.3 "MOMO: Scheduling Method for Large Data Flow Graph", J. Noel, Ch. Trullemans, UCL/DICE, Belgium.

2.4 "Area/Time/Power Space Exploration in Module Selection for DSP High Level Synthesis", S. Gailhard, O. Sentieys, N. Julien and E. Martin, IUP-LESTER, France.

14:00 - 15:30 SESSION 3: IC's Design Techniques and Tools
  Chair: J. Figueras

3.1 "High-level Analog/Digital Partitioning in Low Power Signal Processing Applications", S. Donnay, G. Gielen and W. Sansen, K.U.Leuven, ESAT-MICAS, Belgium.

3.2 "Leakage Power Reduction for Reactive Computation", M. Favalli and C. Metra, DEIS - University of Bologna, Italy.

3.3 "CONNAN: A Computer-Aided Design Tool based on Sharing Information for Analog Circuit Sizing", D. Marin, J. Escudero and D. Flandre, UAB - Unitat de Microelectronica, Spain.

3.4 "Mixed Direct Search and Monte-Carlo Techniques produce Fast and Robust IC Parametric Yield Estimates", J. Horan and C. Lyden, Cork Regional Techn. College, Ireland.

16:00 - 17:30 SESSION 4: Logic Level Synthesis
  Chair: C. Svensson

4.1 "Carry Circuit Depth Optimization by BDD Based Decomposition", A. Kornilov, T. Isaeva and V. Syngaevsky, NIISAPRAN, Academy of Sciences, Russia.

4.2 "Switch-level Technology Mapping and Modeling", J. Riera, J. Velasco, L. Ribas and J. Carrabina, UAB - Unitat de Microelectronica, Spain.

4.3 "A Rapid Boolean Technology Mapping applicable to Power Minimization", R. Ferreira, A-M. Trullemans-Anckaert and R. Jacobi, UCL/DICE, Belgium.

4.4 "A Strategy for Low Power FSM Design by Reducing Switching Activity", M. Koegst, G. Franke, S. Rulke and K. Feske, Fraunhofer-institut fur Integrierte Schaltungen, Germany.

5.1 "A New Method for Switching Activity Estimation of Logic Level Networks", S. Theoharis, G. Theodoridis, D. Soudris and Goutis, VLSI Design Lab., University of Patras, Greece.

5.2 "Sensitivity of the Worst Case Dynamic Power Estimation on Delay and Filtering Models", S. Manich and J. Figueras, Universitat Politecnica de Catalunya, Spain.

5.3 "Analytical Modelling of Spurious Transitions in Adder Circuits", S.J. Abou-Samra and A. Guyot, INPG/TIMA, France.

5.4 "Application of Toggle-based Power Estimation to Module Characterization", G. Jochens, L. Kruse and W. Nebel, University of Oldenburg and OFFIS, Germany.

11:00 - 12:30 SESSION 6: Panel : "Timing and Power within the Design Flow: Present and Future"

Moderator: Prof. Bruno Riccò
Panelists:

A-M. Trullemans, S. Malik, G. Gielen, R. Zafalon, J. Sparsoe, W. Nebel.

Lunch break

14:00 - 15:30 SESSION 7: Asynchronous Circuits Design
  Chair: J. Sparsoe

7.1 Invited talk: "Power Estimation and Synthesis in the Industrial Perspective", Roberto Zafalon, SGS-Thomson, Italy.

7.2 "A New CMOS Ternary Logic Design for Low-power Low-voltage Circuits", R. Mariani, F. Pessolano and R. Saletti, DII:EIT University of Pisa, Italy.

7.3 "An Innovative Multiple-valued Asynchronous Approach to System Design technique", F. Pessolano, R. Mariani and R. Saletti, DII:EIT - Univerity of Pisa, Italy.

7.4 "Area Reduction in Asynchronous Circuits by Signal Transition Graph Transformations", G.S. Panagiotaras, O.G. Koufopavlou, VLSI Design Laboratory, University of Patras, Greece.

16:00 - 17:30 SESSION 8: Device Level Modeling
  Chair: B. Riccò

8.1 "A Physically Based I-V Model of Partially Depleted SOI MOSFET's dedicated to Deep Sub-micron VLSI/CMOS Technologies", P. Flatresse, O. Faynot and J.L Pelloie, LETI (CEA-Tech. Avancees), France.

8.2 "Delay Degradation Effect in Submicronic CMOS Inverters", J. Juan-Chico, M.J. Bellido, A.J. Acosta, A. Barriga and M. Valencia, Instituto de Microelectronica de Sevilla CNM, Spain.

8.3 "A Method to extend the Validity of Quasi-static SOI MOSFET Models", L.F. Ferreira, D. Flandre and P. Jespers, UCL/DICE - Belgium.

8.4 "Substrate Coupling Trends in Future CMOS Technologies", X. Aragones, J.L. Gonzalez and A. Rubio, Universitat Politecnica de Catalunya, Spain.

20.30 Evening banquet

9.1 "Glitch Current Peak Estimation in CMOS Gates", G. Zuo and N. Rumin, DEE - McGill University, Canada.

9.2 "Signal Transition Modeling in Submicronic CMOS Structures", J-M. Daga and D. Auvergne, LIRMM - Université Montpellier, France.

9.3 "On estimating Leakage Power Consumption for Submicron CMOS Digital Circuits" A. Ferré and J. Figueras, Universitat Politecnica de Catalunya, Spain.

9.4 "Estimation of Short-circuit Power Dissipation for Static CMOS Gates driving a CRC Pi Load" A. Hirata, H. Onodera and K. Tamaru, Kyoto University, Japan.

11:00 - 12:30 SESSION 10:Open discussion : "1% Accuracy on what? The Need of Benchmarks for Power Estimation"

Moderator: Michele Favalli

Several works are addressing the problem of power estimation at different abstraction levels, the lack of common benchmarks, however, makes it difficult to compare different techniques. PATMOS participants are called to provide their qualified contribution about this topic.

Lunch break

14:30 - 16:00 SESSION 11: Interconnections and Performance Modeling
  Chair: D. Auvergne

11.1 "Delay Propagation Term for Submicron Interconnect", E. Vanier and D. Deschacht, LIRMM - Université Montpellier, France.

11.2 "A Wire Capacitance Estimation Technique for Power Consuming Interconnections at High Levels of Abstraction", A. Alvandpour and C. Svensson, University Linköping, Sweden.

11.3 "Probability Based Delay Analysis and Tuning of VLSI Circuits using a Variance-Covariance Method", I.J. Osele and R. Sridhar, The State University of New York at Buffalo, USA.

11.4 "Performance Analysis and Propagation Delay Time Estimation of Logic Families with HBTs", J. del Pino, A. Hernandez, J. Garcia, B. Gonzalez and A. Nunez, Universidad de Las Palmas de Gran Canaria, Spain.

16:00 - 17:30 SESSION 12: High Level Views of Power Dissipation
  Chair: S. Jones

12.1 "Cosimulation for Ultra Low Power Systems" J.P. Meunier, Steven Chau and Marty Rana, Synopsys PTG, USA.

12.2 "High Level Power Estimation", R. Peset Llopis, Philips Research Laboratories, The Netherlands.

12.3 "Energy Complexity & Architecture", J. Smit, University of Twente, The Netherlands.

12.4 "If-Diagrams: Theory and Application", A. Prihozhy, State University of Informatics & Radioelectronics, Belarus.

17:30 - 18:00 CLOSING

Chairs: A.-M. Trullemans, B. Riccò

About Louvain-la-Neuve

By car:
From Brussels: Take the E411 motorway towards Namur-Luxembourg. At Exit 7, "Louvain-la-Neuve", follow the N4, and after 2.5 km, turn right off the N4 at the second roundabout (Louvain-la-Neuve Centre).
From Namur: Take the E411 motorway towards Brussels. At exit 9, "Corroy-le-Grand/Louvain-la-Neuve", turn left towards the N4. Turn right on the N4, and left it on the first roundabout (Louvain-la-Neuve Centre).

By train: From any station in Brussels, ask for a ticket to "Louvain-la-Neuve-Université" (NOT Louvain/Leuven), and take the Brussels-Ottignies-Namur-Luxembourg line.
If you want to go by taxi from the station to your hotel in Louvain-la-Neuve or in Wavre, ask for a ticket to "Ottignies" (the station 5 minutes before Louvain-la-Neuve), and ask there for a taxi.

By plane: Fly to Brussels National Airport (Zaventhem). The airport is linked to Brussels (Central or North station) by a train service every 20 minutes (10 minutes travel). From these stations you could reach Louvain-la-Neuve by train (2 trains per hour, about 30 minutes travel). A taxi from the airport to Louvain-la-Neuve costs approximately 2 500 BEF.

Bank transfer should be made free of any charge to
ARAMIS, Place du Levant, 3 B-1348 Louvain-la-Neuve

- Name of the Bank :   General Bank

- Address of the Bank :   Place de l'Universite, 6, B-1348 louvain-la-Neuve

- Account number :   271-0315085- 61

- Swift code :   GEBA BE BB 03A (Charleroi, Main Branch).

Credit card facilities are also available, and the following cards are accepted for payement: Visa, Mastercard or Eurocard.

Cancellations will only be accepted if made in written form to the PATMOS'97 secretariat. Registration cancelled before August, 18 will be refunded 80% of the fees paid. Latter cancellation will be charged full fees. Substitution can be made at any stage.

Registration fees:

before August 18 :   13.500 BEF
after August 18 :   15.000 BEF
companion banquet ticket :   2.000 BEF

admittance to the workshop
one copy of the proceedings
lunches and coffee breaks
visit and cocktail on Monday evening
banquet on Tuesday evening

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(before Aug. 18: 13 500 BEF, after Aug. 18: 15 000 BEF)

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(2000 BEF per additional ticket)

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Payement by bank tranfer  

Bank transfer should be made in BEF, free of any charge to

ARAMIS, Place du Levant, 3 B-1348 Louvain-la-Neuve

Account number   271-0315085- 61 - Swift code   GEBA BE BB 03A

Please state clearly "PATMOS 97" and the name of participant on the bank transfer form.

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• Hotel Le Rocher ***

  Located in an oasis of green, "Le Rocher" offers both elegance and an enviably strategic location. The warmth and refinement of the interior is vey different from the sterile atmosphere so typical of traditional meeting venues. At "Le Rocher", business becomes a pleasure. 5'from Louvain-la-Neuve. The transport will be organised to the conference place each morning.

  Address: Chaussée de Namur 221, 1300 Wavre.
  Phone : +32 (0) 10 45 41 44 - Fax : +32 (0) 10 41 97 33

  Prices:
  

  Single room :   2 500 BEF
  Double room :   2 950 BEF
  
  

• Hotel de Lauzelle ***

  Hotel de Lauzelle offers a unique setting of peacefulness and well-being. It is the tradition of Hospitality. 10' walking from the conference place.

  Address: Avenue de Lauzelle 61, 1348 Louvain-la-Neuve
  Phone: +32 (0) 10 45 07 51 - Fax: +32 (0) 10 45 09 11

  Prices:
  

  Single room :   2 550 BEF
  Double room :   2 900 BEF
  
  All prices include breakfast

• Hotel Eurovillage ***

  Hotel Eurovillage offers comfortable bedrooms with bath, television, video... VIP and non-smoking-room may be reserved. Ample parking, shopping area, health club, sauna, garden, terrace are at your disposal. Eurovillage is located in Brussels 5' walking from the Schumann railway station (35 minutes train to Louvain-la-Neuve).

  Boulevard Charlemagne 80, 1000 Bruxelles.
  Phone: + 32 (0) 2 230 85 55 - Fax: +32 (0) 2 230 56 35

  Prices:
  

  Single room :   4 050 BEF
  Double room :   5 100 BEF

Hotel de Lauzelle (Fax : +32 (0) 10 45 09 11)  
Le Rocher ( Fax : +32 (0) 10 41 97 33)  
Eurovillage (Fax : +32 (0) 2 230 56 35)  

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