International Workshop - Power and Timing Modeling, Optimization and Simulation
Technical University of Denmark - October 7 - 9, 1998
What is PATMOS?
The workshop is the eighth of a series of international workshops having been held in Kaiserslautern, Germany, 1991, Paris, France, 1992, Montpellier, France, 1993, Barcelona, Spain, 1994, Oldenburg, Germany, 1995 and Bologna, Italy, 1996, Louvain-la-Neuve, Belgium, 1997. PATMOS has over the years evolved into a well established and outstanding series of open European events on power and timing of integrated circuit design. The increased interest especially in low-power design gives an additional momentum to the interest in this workshop. Despite its growth, the workshop can still be considered as an informal but very focused conference featuring high level scientific presentations together with open discussions and panel sessions in a free and easy environment. In 1998 the venue will be at the Technical University of Denmark.
The objective of this workshop is to provide a forum in which to discuss
and investigate the emerging problems in the design methodologies and CAD-tools
for the new generation of IC technologies. A major emphasis of the technical
program is on speed and low-power aspects with particular regard to modeling,
characterization, design, and architectures. The scope of the workshop
includes, but is not limited to, design and CAD aspects of:
Back to front.
Low-power design: high performance low power systems, ultra low
power systems, special architectures.
Modeling and synthesis: timing, power, low-voltage, interconnect,
Timing design: clocking, synchronization, asynchronous and self
timed systems, adiabatic switching.
Optimization: low voltage low power logic families, logic parallelization,
pipelining, fast low power arithmetic.
Physical design: module generation, library optimization and characterization,
Physical test and characterization: low VT low voltage processes,
SOI, IDDQ, models and parameter extraction, experimental design for process
Design methods and CAD tools for low-voltage low-power design, high-speed
Trade-offs between devices, architectures and technologies, benchmark comparison.