FAQ on Xputers - Xputer Lab Kaiserslautern - Reconfigurable Computing with KressArray
[ > | Xputer Lab | Xputer literature | Xputer Directory | Xputers: FAQ&FQA | Xputers: AQ(1) | Xputers: FAQ (3 ) | Data Sequencers | Kress Array | Xputers: FQA Intro | Xputer Lab History | What's new? ]

Xputers: FAQ (2)

Xputers: FAQ(1)


Xputers: FAQ (1)

Several sequencers in one machine?
What is a Map-oriented Machine (MoM)?
What is the Kress Machine?

Xputers: FAQ (3)

Several sequencers in one machine?

If you are not familiar with Xputers, first see special page explaining all about data sequencers. In a von Neumann machine you may have only one sequencer. But the Xputer paradigm permits to have several sequencers in a single machine [1]. This, for example makes sense not only in a number of DSP algorithms, such as FFT (Fast Fourier Transforms), like the constant gemometry FFT. Fig. 5 illustrates the use of three data seuqencers for a 16 point constant gemometry FFT. The 2-by-2 scan window no. 1, sequenced by sequencer no. 1, communicates throug the data path with scan windows no. 2 and 3. A scan window is a kind of smart register file. Fig. 24 illustrates, how the 3 scan windows are sequenced throutgh memory space.

< >Fig. 5. Constant Geometry FFT using 3 Sequencers

What is a Map-oriented Machine (MoM)?

The MoM (Map-oriented Machine) is an Xputer architecture based on 2-dimensional memory organization. A MoM features 2-dimensional scan windows, size adjustable at run time. A scan window buffers a 2-dimensional memory subspace, such as 2 by 3 words, for example (see section 3 of FAQ on Xputers). The scan window is implemented by a smart processor-to-memory interface (see figure 6), which is a smart register file featuring various aids to save memory access cycles [2]. 2D memory space supports excellent visualization of computations and data dependencies [3].

< >Fig. 6. Basic Structure of the MoM Xputer Architecture:

[rDPA: see Kress Array | how SMIF accelerates]

How the SMIF accelerates by saving memory cycles

With progress of technology the processor / memory communication gap widens more and more. Even very large caches cannot bridge this gap completely. Caches accelerate only software with highly iterative loops on write once (into cache) and read very often (from cache). Cache efficiency is probabilistic, and is very low for a number of important algorithms. For Xputers, however, caches do not help at all, since Xputers' compilers convert loops into hardware configurations. In this context the smart memory interface (see fig. 6) uses deterministic methods to reduce the number of memory cycles - compared to a von Neumann implementation of the same algorithm [2].

< >Fig. 7. Xputer Architectures - The Kress Machine:

[All about Data Sequencers | rDPA: see Kress Array]

What is the Kress Machine?

The Kress Machine is a novel MoM Xputer Architecture (see figure 7) [thesis]. Instead of a rALU (reconfigurable ALU), i. e. a reconfigurable Data Path (rDP), it has an array of rDPs (an array of rALUs), called rDPA (reconfigurable Data Path Array) [4]. Instead of a single ALU the Kress Machine (see fig. 8) uses a RDPA as an ALU Array (Kress Array). Rainer Kress has also implemented a routing and placement tool DPSS to map expressions onto rDPAs. For more details special page on the Kress Machine.

< >Fig. 8. Basic Structure of the Kress Machine:

Xputer Literature

[1] A. Ast, R. W. Hartenstein, H. Reinig, K. Schmidt, M. Weber: A General Purpose Xputer Architecture derived from DSP and Image Processing; in M.A. Bayoumi (ed.): VLSI Design Methodologies for Digital Signal Processing Architectures, Kluwer Academic Publishers, p. 365-394, 1994.
[2] R. Hartenstein, R. Hauck, A. Hirschbiel, W. Nebel, M. Weber: PISA, a CAD package and special hardware for pixel-oriented layout analysis; Proceedings ICCAD - Int'l. Conf. on CAD, Sta. Clara, California, 1984.
[3] R. Hartenstein, A. Hirschbiel, M. Weber: MOM - Map Oriented Machine; Proceedings of the International Workshop on Hardware Accelerators, Oxford, 1987.
[4] R. Hartenstein, R. Kress: A Datapath Synthesis System for the Reconfigurable Datapath Architecture; Proc. Asia and South Pacific Design Automation Conference (ASP-DAC'95), Makuhari, Chiba, Japan, Aug. 29 - Sept 1, 1995

Xputers: FAQ (3)

You have more questions on Xputers? You have better questions?

If yes, please, inform our webmaster. Our goal is the steady improvement of this list of questions.

[ Xputer Lab | Xputer literature | Xputer Directory | Xputers: FAQ&FQA | Xputers: FAQ (1) | Xputers: FAQ (3) | Data Sequencers | Kress Array | Xputers: FQA Intro| Xputer Lab History | What's new? | Key words on Xputers ]

© copyright 1996, Xputer Laboratory, Universitaet Kaiserslautern, Kaiserslautern, Germany ----- Webmaster