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Xputers: FQA (3):


Xputers: FQA (1)
Xputers: FQA (2)

Xputers and Hardware/Software Co-Design
Xputers and C
ustom Computing Machines
Xputers and Application-specific Processors
Xputers and ASIPs
Xputer Applications
The Xputer: more than just a General Purpose Accelerator

Xputers and Hardware/Software Co-Design

Hardware/Software Co-Design [1] has the goal to optimize the hardware/software trade-off in Partitioning an application problem into a software part (to run on the host) and an add-on accelerator hardware part. Researchers complaint [2] that a general model is missing, which brings the very wide variety of architectures under a common umbrella. The Xputer paradigm has the potential to be such a general model of hardware/software co-design (see here).

Xputers and Custom Computing Machines

The design of custom computing machines [3] [4] is similar to hardware/software co-design. The main difference is the use of fied-rgramabe ccelerators, whereas hardware/software co-design prefers hardwired add-om accelerators. Also here the Xputer paradigm has the potential to be a general model of hardware/software co-design (see here), which bridges the many gaps between the very wide variety of architectures.

Xputers and Application-specific Processors

For implementing Application-specific accelerators a hardware experts are needed, even for FPGA-based custom somputing machines. Compilers accepting programming languages are not available for synthesis, so that these ommercially available platforms are far from the dream of software-only implementation of accelerators. The ASIP approach redesigns everything (see next section), even compiler and operating system are application-specific - a huge effort, as long as a very powerful repertory of generators is not available. Custom computing machines [3] [4] are a tinker toy approach not permitting a systematic compilation environment. What we need are general purpose accelerators - technology platforms suitable for being supported by a novel class of application development tools. compilation techniques. The key issue on the way to implementation [5] of accelerators are general purpose compilation techniques instead of specialized compilers. We believe, that Xputer-based platform architectures are the best basis of general purpose compilers for software-only accelerator implementation.

Xputers and ASIPs

ASIPs (Application-specific Instruction Set Processors [6] [7] ) are developped by experimenting with alternative processor architectures for particular application samples. Their alternative perfornce data are derived by profiling from simulation. Each alternative requires a complete processor design, so that there is no compatibility to existing software of any kind. That's why an ASIP development environment should have a bunch of generators like an architecture generator, a compiler generator, operating system generator, and a simulator generator. Also see: Application-specific Processors and Xputers

Xputer Applications

Xputers provide high speed-up factors for all applications with halfways or fully regular data depencencies, such as in DSP, image processing, most scientific applications and many others. For more details see section FQA on Xputers.

The Xputer: more than just a General Purpose Accelerator

The Xputer may also be used in stand-alone mode. E. g. this makes sense in embedded systems and in many other eapplication environments with high cost/performance trade-off requirements. Xputers are used as central units, the CPUs. This means an accelerator without a host: really a full paradigm switch. Also see software-only accelerators.

H/S migration to R/C time migration

The usual add-one hardware provides speed-up by software to hardware migration. In addition to his Xputers provide further speed-up by runtime to compile time migration (RT2CT migration). This is shown by comparative overhead analysis. An example is comples address computation (see fig. 26), which ona vonNeumann implementation has to be carried out at run time, whereas on an Xputer this may be done by compiling reconfiguration code to be downloaded into a data sequencer. In a grid-based design rule check implementation, for example, this has contributed one and half order of magnitude to speed-up (see fig. 26).


[1] K. Buchenrieder: Hardware/Software Co-Design - an annotated bibliography; ITpress Verlag 1994
[2] R. Gupta: Hardware/Software Co-Design of Embedded Systems; Tutorial on the 9th Int'l. Conf. on VLSI Design, Bangladore, India, Jan. 1996.
[3] Reiner W. Hartenstein (opening key note): Custom Computing Machines - An Overfiew; Workshop on Design Methodologies for Microelectronics, Smolenice Castle, Slovakia, September 1995.
[4] Reiner W. Hartenstein, Juergen Becker, Rainer Kress: Custom Computing Machines vs. Hardware Software Co-Design: from a globalized point of view; 6th International Workshop On Field Programmable Logic And Applications, FPL'96, Darmstadt, Germany, September 23-25, 1996, Lecture Notes in Computer Science, Springer Press, 1996.
[5] Reiner W. Hartenstein, Juergen Becker: A Two-level Co-Design Framework for data-driven Xputer-based Accelerators; to be published in Proc. of 30th Annual Hawaii Int. Conf. on System Science (HICSS-30), January 7-10, Wailea, Maui, Hawaii, USA, 1997.
[6] J. Sato, M. Imai, T. Hakata, A. Y. Alomary, N. Hikichi: An Integrated Design Environment for Application Specific Integrated Processor; Proc. of IEEE Int'l. Conf. on Computer Design: ICCD 1991, pp. 414-417, Oct. 1991.
[7] Ing-Jer Huang, A. Despain: Synthesis of Application Specific Instruction Sets; IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 14. No. 6, June 1995.

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