FAQ on Xputers - Xputer Lab Kaiserslautern - Reconfigurable Computing with KressArray

[ ð | Xputer Lab | Xputer literature | Xputer FAQ Directory | FAQ&FQA on Xputers | FAQ1 on Xputers | FAQ2 on Xputers | FAQ3 on Xputers | Data Sequencers | Kress Array | FQA on Xputers | History of the Xputer Lab | Xputer Books ]  

Call for Partners - New Horizons in R&D

What's new ?

A dream has become reality

We open a bottle of Dom Perignon !

Multibank DRAM Chips available commercially. The high performance of our MoM Xputer architecture has increased the processor to memory bandwith gap by another order of magnitude. Another bad news had been, up to now, that caches do not work with many efficient Xputer applications - because of memory access reduction by loop transformations. So we urgently needed interleaved memory access, which had been very expensive. Now the solution is on board of the memory chip.
We just received specs of Siemens Multibank DRAM. The 9MBit chip of type MYB30M93200 has 36 banks and permits a peak data rate of 666 MBytes/sec.

Manufacturers: [ Oki | Siemens ]

 
[ Xputer Lab | Xputer literature | FAQ&FQA on Xputers | Xputer FAQ Directory | FAQ1 on Xputers | FAQ2 on Xputers | FAQ3 on Xputers | Data Sequencers | Kress Array | FQA on Xputers | History of the Xputer Lab | Xputer Books ]



© copyright 1996, Universitaet Kaiserslautern, Kaiserslautern, Germany ----- Webmaster