FPL96 Program - Reconfigurable Computing with KressArray
FPL'96 Final Program:
- Monday, Sep. 23
- 8.00 - 9.00 Registration
- 9.00 - 9.30 Opening Session
- 9.30 - 10.20 Session 1: High-level
Design I
- 10.20 - 10.35 Coffee Break
- 10.35 - 12.15 Session 2: New
SW and HW Development Tools
- 12.15 - 14.00 Lunch
- 14.00 - 15.40 Session 3:
Custom Computers
- 15.40 - 16.15 Coffee Break
- 16.15 - 17.30 Session 4:
High-level Design II
- 19.00 - 20.00 Reception
- 20.00 - 23.00 Social evening
at own expense
- Tuesday, Sep. 24
- 8.30 - 10.10 Session 5: Applications
- 10.10 - 10.35 Coffee Break
- 10.35 - 11.50 Session 6:
Hardware/Software Co-Design
- 11.50 - 12.40 Session 7:
ASIC Emulators etc.
- 12.40 - 14.20 Lunch
- 14.20 - 15.25 Poster presentation
- 15.25 - 16.40 Session 8 (parallel
to S. 9): Poster session: see separate column.
- 15.25 - 16.40 Session 9 (parallel
to S. 8): Vendor session
- 16.40 - 17.10 Coffee Break
- 17.10 - 18.25 Session 10:
Industrial Applications and Experiences
- 19.30 Banquet in the Guesthouse
of the Darmstadt University of Technology
- Wednesday, Sep. 25
- 8.30 - 10.10 Session 11:
Reconfiguration Aspects
- 10.10 - 10.35 Coffee Break
- 10.35 - 12.40 Session 12:
CAD user experiences
- 12.40 - 12.50 Closing Session
- Announcement of the location of FPL'97
- Poster session (Session
8)
- on Tuesday, Sep. 24, 15.25
- 16.40
Monday, Sep. 23
8.00 - 9.00 Registration
9.00 - 9.30 Opening Session
9.30 - 10.20 Session 1: High-level Design I
- M.Weinhardt; U Karlsruhe (D):
- Portable Pipeline Synthesis for FCCMs
- C.Legl, K.Eckl, B.Wurth; TU Munich (D):
- Performance-Directed Technology Mapping for LUT-Based FPGAs - What
Role do Decomposition and Covering Play?
10.20 - 10.35 Coffee Break
10.35 - 12.15 Session 2: New SW and HW Development Tools
- W.Luk, S.Guo, N.Shirazi, N.Zhuang; IC London (UK):
- An Integrated Framework for Developing Parametrised Macros
- T.Miyazaki, A.Tsutsui, K.Ishii, N.Ohta; NTT Labs (JP):
- FACT: Co-evaluation Environment for FPGA Architecture and CAD System
- J.Stohmann, E.Barke; U Hannover (D):
- An Universal CLA Adder Generator for SRAM-Based FPGAs
- Y.Shibata, X.Ling, H.Amano; Keio U (JP):
- An Emulation System of the WASMII: a Data Driven Computer on a Virtual
Hardware
12.15 - 14.00 Lunch
14.00 - 15.40 Session 3: Custom Computers
- R.W.Hartenstein, J.Becker, R.Kress; U Kaiserslautern (D):
- Custom Computing Machines vs. Hardware/Software Codesign: from a globalized
point of view
- S.Ludwig; ETH Zurich (CH):
- The Design of a Coprocessor Board Using Xilinx's XC6200
- D.Smith, D.Bhatia; U Cincinnati (USA):
- RACE: Reconfigurable Adaptive Computing Environment
- C.H.Dick; LaTrobe U (AUS):
- Computing 2-D DFTs using FPGAs
15.40 - 16.15 Coffee Break
16.15 - 17.30 Session 4: High-level Design II
- U.Ober, H.J.Herpel, M.Glesner; TH Darmstadt (D):
- CAPpartx: Computer Aided Prototyping Partitioning for Xilinx FPGAs,
a Hierarchical Partitioning Tool for Rapid Prototyping
- D.W.Trainor, R.F.Woods; The Queen's U Belfast (UK):
- Architectural Synthesis and Efficient Circuit Implementation for Field
Programmable Gate Arrays
- C.Ebeling, D.Cronquist, P.Franklin; U Washington (USA):
- RaPiD - A Reconfigurable Pipelined Datapath
19.00 - 20.00 Reception
20.00 - 23.00 Social evening at own expense
Tuesday, Sep. 24
8.30 - 10.10 Session 5: Applications
- T.Suyama, M.Yokoo, H.Sawada; NTT Labs (JP):
- Solving Satisfiability Problems on FPGAs
- C.Sanz, L.deZulueta, J.M.Meneses;TU Madrid (E):
- FPGA Implementation of the Block-Matching Algorithm for Motion Estimation
in Image Coding
- T.Gruen, J.Lembert; U Saarbruecken (D):
- Parallel CRC Computation in FPGAs
- U. Meyer-Baese; U Florida (USA):
- Coherent Demodulation with FPGAs
10.10 - 10.35 Coffee Break
10.35 - 11.50 Session 6: Hardware/Software Co-Design
- S.Gehring, S.Ludwig; ETH Zurich (CH):
- The Trianus System and its Application to Custom Computing
- N.Lester, J.Saul; U Oxford (UK):
- Logic Synthesis for FPGAs Using A Mixed Exclusive- / Inclusive-OR Form
- K.Tammemaee, M.O'Nils, A.Hemani; KTH Kista (S):
- Flexible codesign architecture for early prototyping of CMIST systems
11.50 - 12.40 Session 7: ASIC Emulators etc.
- K.Inoue, T.Kisuki, M.Okuno, E.Shimizu, T.Terasawa, H.Amano; Keio U
(JP):
- ATTEMPT-1: A reconfigurable multiprocessor testbed
- N.Janzen, F.J.Rammig; U Paderborn (D):
- A Slow Motion Engine for the Analysis of FPGA-Based Prototypes
12.40 - 14.20 Lunch
14.20 - 15.25 Poster presentation
15.25 - 16.40 Session 8 (parallel to S. 9): Poster session: see separate
column.
15.25 - 16.40 Session 9 (parallel to S. 8): Vendor session
- A.Hesener; Atmel Corp. (D):
- Implementing reconfigurable datapaths in FPGAs for adaptive filter
design
- T.Kean, B.New, B.Slous; Xilinx Corp.(UK):
- A Multiplier for the XC6200
- A.Ditzinger; ISDATA GmbH Karlsruhe (D):
- Key features for user acceptrance of FPGA design tools
16.40 - 17.10 Coffee Break
17.10 - 18.25 Session 10: Industrial Applications and Experiences
- B.L.Combridge, P.S.Cornfield, S.Naunton; Matra Marconi Space (UK):
- Reconfigurable DSP Demonstrators for the Development of Spacecraft
Payload Processors
- S.Casselman; Virtual Computer Corp. (USA):
- Reconfigurable Logic Based Fibre Channel Network Card With Sub 2 Micro-Second
Raw Latency
- J.R.Haddy, D.J.Skellern; Macquarie U (AUS):
- An Asynchronous Transfer Mode (ATM) Stream Demultiplexer and Switch
19.30 Banquet in the Guesthouse of the Darmstadt University of Technology
Wednesday, Sep. 25
8.30 - 10.10 Session 11: Reconfiguration Aspects
- M.Vasilko, D.Ait-Boudaoud; U Bournemouth (UK):
- Optically Reconfigurable FPGA: Is this a future trend?
- Z.Salcic, B.Maunder; U of Auckland (NZ):
- CCSimP - an Instruction-Level Custom-Configurable Processor for FPLDs
- M.Vasilko, D.Ait-Boudaoud; U Bournemouth (UK):
- Architectural Synthesis Techniques for Dynamically Reconfigurable Logic
- H.Eggers, P.Lysaght, H.Dick, G.McGregor; U Strathclyde (UK):
- Fast, Reconfigurable, Crosspoint Switching in FPGAs
10.10 - 10.35 Coffee Break
10.35 - 12.40 Session 12: CAD user experiences
- G.Yasar, J.Devins, Y.Tsyrkina, G.Stadtlander, E.Millham; IBM (USA):
- Growable FPGA Macro Generator
- J.P.Heron, R.F.Woods; The Queen's U Belfast (UK):
- Physical Optimisation in FPGA's
- G. Brebner; U Edinburgh (UK):
- A Virtual Hardware Operating System for the Xilinx XC6200
- A.Trost, R.Kuznar, A.Zemva, B.Zajc; U Ljubljana (Slovenia):
- An Experimental Programmable Environment for Prototyping Digital Circuits
- M.Gschwind, C.Mautner; TU Vienna (A):
- Migration from schematic-based designs to a VHDL synthesis environment
12.40 - 12.50 Closing Session - Announcement of the location of FPL'97
Poster session (Session 8)
on Tuesday, Sep. 24, 15.25 - 16.40
- A.Balboni, L.Valenti; Italtel (IT):
- ASIC Design and FPGA Design: a unified design methodology applied to
different technologies
- C.H.Dick, F.Harris; LaTrobe U (AUS):
- FIR Filtering with FPGAs Using Quadrature Sigma-Delta Modulation Encoding
- K.Yi, C.S. Jhon; U Seoul (KR)
- A New FPGA Technology Mapping Approach by Cluster Merging
- L.Larsson; U Hamburg (D)
- An EPLD Based Transient Recorder for Simulation of Video Signal Processing
Devices in a VHDL Environment Close to System Level Conditions
- U.Meyer-Baese; U Florida (USA):
- Convolutional Error Decoding with FPGAs
- B.M.Rogina, K.Skala, B.Vojnovic; Rudjer Boskovic Inst. (Croatia):
- Metastability Characteristics Testing for Programmable Logic Design
- K.Rowley, C.Lyden; UC Lee Maltings (EIR):
- Implementing SigmaDelta modulator prototype designs on an FPGA
- J.L.Ruiz, Y.Torroja, J.L.Garcia; TGI Madrid (E):
- Design of a VME Parametrized Library for FPGAs
- G.Schumacher, B.Josko, G.Wagner, M.Radetzki; U Oldenburg (D)
- Development of a telephone answering machine in a lab - FPGAs in education
- V.Tchoumatchenko, T.Vassileva, R.Ribas, A.Guyot; TIMA (F):
- FPGA Design Migration: Some Remarks
- L.Torres, S.Pillement, M.Robert, G.Cambon; U Montpellier 2 (F):
- Concurrent Design of Hardware/Software Dedicated Systems
- A.Touhafi, W.Brissinck, E.Dirkx; FU Brussels (B):
- The Implementation of an FPL Based Co-Processor for the Acceleration
of Discrete Event Simulators
- M.Weinhardt; U Karlsruhe (D):
- Computing Weight Distributions of Binary Linear Block Codes on a CCM
FPL'96 Program - 4 JUN 1996
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