Call for Exhibitors
High Growth Rate
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Call for Papers:  PDF PS

The conference proceedings will be published by Springer Verlag Berlin / Heidelberg / New York -  within the LNCS series (Lecture Notes on Computer Science). See:  http://link.springer.de/series/lncs/
Also see earlier FPL volumes and: Instructions to Authors

              General Chair:
              Herbert Gruenbacher
              Carinthia Tech Institute
           mailto:hg@cti.ac.at

              Program Chair:
              Reiner Hartenstein
              Kaiserslautern University
           mailto:hartenst@rhrk.uni-kl.de
 

Download Call and Registration Form : PDF/ Postscript

The New Case for Reconfigurable Platforms: Converging Media. As PCs, laptops,
palmtops, consumer electronics, voice, sound, video, TV, wireless, cable, telephone and
internet continue to converge, new opportunities for reconfigurable platform applications are
arising. The new converged media require high volume flexible multi-purpose multi-standard low
power products adaptable to support evolving standards, emerging new standards, field upgrades,
bug fixes, and, to meet zillions of individual subscribers' different preferred media mixes.

Frustration on Networking Applications? There is a frustrating difference between usage and publications on reconfigurables in networking and wireless applications. There is a worldside urgent need on papers about these and related topic areas. Submit ! - P.S. This wake-up call has been successful. FPL-2000 has papers on this areas - as the first conference in the field!

Frustration on Wireless Communication Applications ? See above.

Goals and Scope. FPL-2000 has the goal to provide a review of the work of the past millennium and not only a look forward to what we can expect in the beginning new milennium, but also to present the roadmap to next generation reconfigurable systems (RS) and their application: hardware, configware, software and application development tools (including genetic algorithms), intellectual property cores, system-on-chip  design, as well as RS technology. It is an important goal of the conference, to bring together experts and students from industry and academia.

Technologies for Adaptive Systems
Low Power reconfigurable circuits and systems
FPGA Architectures
Customizable Computing Engines
Embedded Reconfigurable Systems
Fault tolerance by Reconfigurability

FPGA and RCS* Applications:
Networking and wireless communication applications
Evolvable hardware real-world applications
Rapid-prototyping

CAD for FPGA and RC* application development
Interconnect Design and Parameter Estimation
Design Flow
High Level and integrated application development
Testing, Verification and Benchmarking of Reconfigurable Systems

The Roadmaps to Technology, Application and Design
Teaching Reconfigurable Systems and Evolutionary Computation
History of Reconfigurable Logic, Reconfigurable Computing and Evolvable Hardware
Publicity of reconfigurable hardware and its applications
Tutorials
Design Contest,Student Designs

Evolvable Hardware (EH)
Co-Evolution - Hardware/software co-evolution
Tools and methodologies supporting evolvable hardware (EH)
Genetic Programming for Reconfigurable Platforms

State machines and Cellular Automata
Biologically inspired and brain inspired hardware

Contents

Summary of Objectives

Information to Authors

Organization

Schedule

Advance Program

Conference Place

About the FPL Conference series

Topic Areas in Detail.

• Technologies for Adaptive Systems
• Novel device architectures
• New techlogies for reconfigurability
• Emerging technologies for teconfigurability
• Novel reconfigurable interconnect structures
• Low Power reconfigurable circuits and systems
• Design flows for low power and high performance objectives
• Circuit and interconnect techniques for low power
• Evaluation of area / power / performance trade-off
• Programmable multiplexer-based interconnect design
• Genetic programming for logic synthesis with multiplexers
• FPGA Architectures
• Logic block & routing architectures, I/O
• communication architectures, reconfigurable fabric
• new architectures: commercial and research
• Field-Programmable Interconnect Chips and Devices (FPIC/FPID),
• Field-Programmable Analog Arrays (FPAA).
• survey papers on FPGA architectures
• Reconfiguration Architectures and Self-Reconfigurable Architectures
• Customizable Computing Engines
• Reconfigurable custom computing machines
• Reconfigurable accelerators and their applications
• Adaptive hardware, adaptive computing system
• Compiled accelerators, reconfigurable computin
• adaptive computing devices, systems and software
• Coarse grain reconfigurable architectures
• Novel machine and system architectures
• performance- / resolution-adjustable architectures
• Embedded Reconfigurable Systems
• Microprocessor/FPGA hybrid devices
• Hardware/configware/software co-design
• Partially reconfigurable designs
• FPGA-based space applications
• Fault tolerance by Reconfigurability
• Remote repair, self repair, fault tolerance and reliability by reconfiguration
• Self-Repairing and Evolvable Hardware using Self-Configuration
• Dynamically adjustable fault tolerance
• Reliability analysis in self-repairing systems
• FPGA applications in unknown, harsh and/or changing environments

• FPGA and RCS* Applications:
• Applications from a wide variety of areas
• Industrial applications and experiences
• Innovative use of FPGAs,
• Communications system and internet applications
• human-oriented hardware interfaces
• automotive and aerospace applications
• high-performance/ low-power/mission-critical applications,
• Using massively Parallel Self-Reconfigurable Architectures
• Speed-up effects
• Survey papers
• Networking and wireless communication applications
• Data transfer optimization by reconfigurables
• Java processing on reconfigurable platforms
• 3G and 4G software radio with reconfigurables
• Rake receivers using reconfigurable hardware
• Evolvable hardware real-world applications
• Application of Evolvable and adaptable systems
• Adaptive automotive and flight hardware
• systems for space missions and defense applications
• systems in hostile environments
• Commercial applications of evolutionary algorithms
• Rapid-prototyping:
• Fast prototyping for system level design
• ASIC emulators, hardware modellers and compiled accelerators
• Tools and methodologies for fast prototyping
• Prototyping in an engineering process
• Prototyping of embedded systems
• Prototyping of real-time systems
• The role of FPGAs in system prototyping
• Evolutionary prototyping on reconfigurable platforms

• CAD for FPGA and RC* application development:
• Synthesis challenges by next generation reconfigurables
• Partitioning, placement and routing,
• Technology mapping and logic optimization
• RC module generators,
• CAD for FPGA-based accelerators
• Partially reconfigurable designs
• Configware IPs and IP libraries
• IP-based reconfigurable product development
• Interconnect Design and Parameter Estimation
• a priori, on-line, or a posteriori interconnect parameter estimation
• Wireplanning and logic synthesis
• Physical design (floorplanning, placement and routing)
• Measurement and calibration techniques for interconnect estimation
• Using interconnect estimation algorithms in architecture design and CAD
• Physical design (wire planning, floorplanning, placement and routing)
• Evolution of digital circuits with variable layouts -
• Design Flow
• Design flow in using remote CAD sites
• Design flow in using remote reconfigurable emulation platforms
• Physical design (floorplanning, placement and routing)
• Design flows for low power and high performance objectives
• Design flows for ASIC, MCM and FPGA target technologies
• Architecture evaluation, esp. for microprocessors
• Configware/Software Co-compilation
• Hardware / configware / software codesign and tradeoff
• Retargeting hardware / software co-design methods
• High Level and integrated application development
• Design Space Exploration
• Novel machine paradigms and other general models
• Hardware/Configware/Software Codesign
• Software, configware and hardware development tools
• Configware/Software Co-compilation
• Hardware/Configware/Software tradeoffs
• Related high-level design and compilation research
• Testing, Verification and Benchmarking of Reconfigurable Systems
• Fault modelling on reconfigurable systems
• Testing programmable interconnect structures
• BIST and other testability aids and methods on reconfigurable systems
• Reliability issues in reconfigurable systems
• Benchmarking and profiling
• Device / architecture / technology tradeoffs
• Hardware / configware / software tradeoffs
• Power / performance / area-efficiency tradeoffs

• The Roadmaps to Technology, Application and Design
• Specification for Hardware/Configware/Software Codesign
• Speed-up effects - survey and analysis
• The Future of Reconfigurable Computing Technologies
• Teaching Reconfigurable Systems and Evolutionary Computation
• Reconfigurability in CS and CSE curricula
• Goals of RL and RC education
• Configware / Software Co-Education
• Hardware / Configware / Software Co-Education
• Is there a configware / software culture war in academic curriculum development?
• Dichotomy of procedural vs. structural programming: general impact on curriculum development
• Curriculum issues: theory vs. simulation vs. real time, early vs. late, etc.
• Curriculum issues: genetic algorithms vs. EH* vs. RL* and RC*
• Introductions to reconfigurable logic and systems
• Evolutionary Computation and Using Genetic Programming
• Classification Schemes and Taxonomy
• Teaching reconfigurable systems for school classes
• Laboratory, computer-based, and distance teaching methods
• RL and RC education in non-traditional venues
• Experiences in educational use of internet-based CAD tools (of RL* vendors and others)
• History of Reconfigurable Logic, Reconfigurable Computing and Evolvable Hardware
• Taxonomy and classification schemes, esp. from historical view
• Comparative classification of applications and reconfigurable platforms
• Survey Papers on all aspects of reconfigurable and evolvable systems
• Tutorials with emphasis on the history of RL, RC, and EH
• Publicity of reconfigurable hardware and its applications
• Reconfigurable: why? How to explain to journalists
• Academic curriculum development: a configware / software culture war ?
• Funding programs
• Research and Development Consortia
• Reconfigurability as a topic for high schools
• Configware literacy support by school curricular efforts
• Reporting the media echo of reconfigurable systems
• Tutorials
• Tutorials and demonstrations by hardware and software vendors
• Introductory tutorials on all aspects of reconfigurability
• FPGAs and related hardware platforms
• Application development on reconfigurable platforms
• Tools for application development on reconfigurable platforms
• Prototyping with reconfigurable platforms
• Reconfigurable computing as a paradigm shift
• Microprocessor versus reconfigurable computing
• Embedded systems including reconfigurable platforms
• Tutorials on any other related areas
• Design Contest, Student Designs

• Evolvable Hardware (EH):,
• Evolving hardware systems
• Evolutionary hardware design (also including mechanical systems)
• Novel devices and hardware platforms suitable for evolution
• Evolvable Hardware for Industrial Applications
• On-line or instrinsic evolution of reconfigurable circuits
• Evolutionary experiments with reconfigurable circuits and architectures
• Models for dynamic adaptation in reconfigurable hardware systems
• Evolvable hardware structures by self-configuration
• Co-Evolution - Hardware/software co-evolution
• Co-evolution of hybrid systems (including
• hybrids of wetware, chemical, mechanical, and electronic components, etc.
• Tools and methodologies supporting evolvable hardware (EH):
• Evolution for design and optimization of digital circuits and functions
• Evolutionary design search, exploration and optimisation
• Evolutionary design space exploration beyond conventional methods
• Evolution of circuits in simulation or on reconfigurable hardware
• Evolutionary representations for automatic parallelization
• Genetic Programming for Reconfigurable Platforms
• Evolution by Genetic Programming
• Genetic programming for designing reconfigurable or evolvable hardware
• Evolutionary algorithms for dynamic optimization problems
• Evolutionary representations for automatic parallelization
• Evolution of interconnect and circuits with variable layouts
• Java based distributed genetic programming on the internet

• State machines and Cellular Automata
• Evolution of Cellular Automata
• Induction of State Machines
• State machine and cellular automata application of RL
• Biologically inspired and brain inspired hardware
• Bio-Inspired Hardware
• Brain-Inspired Architectures
• Evolved Neural Net Modules
• Embryonic hardware
• Morphogenesis

Will Reconfigurable Systems overcome the Microprocessor?

The purpose of the workshop is to provide a forum for discussion on the future role of reconfigurable and evolvable hardware in real-world applications, in particular those beyond niche market applications. In the future reconfigurable and evolvable systems may be a threat to the dominating role of microprocessors and microcontrollers. The Workshop attendees will have the opportunity to discuss the fundamental issues and state-of-the art of reconfigurable and evolvable hardware technology, plans for development of future devices and hardware systems suitable for evolution, and needs related to real applications in all areasa.  The outcome of this meeting is expected to be a major contribution to a technology development roadmap that would lead to deployable reconfigurable computing and evolvable hardware .

The scope of this conference encompasses all aspects of reconfigurable computing from hardware design, to compilation   methods, application design and tools. - revealed by bringing together leading researchers and developers from the evolvable hardware community, representatives of the programmable/reconfigurable hardware community, technology developers, and end-users from all present and future application areas, also including communication, automotive and aerospace applications.

Important dates:

submission deadline: March 17, 2000

notification of acceptance: May 14, 2000

deadline for publication-ready pdf files: June 14, 2000

For quotations, please, use:
H. Gruenbacher, R. Hartenstein (Eds.): Field-programmable Logic: The Roadmap to Reconfigurable Systems; Springer Verlag, 2000, Lecture Notes on Computer Science, LNCS (number not yet assigned)

PROGRAM COMMITTEE
 

Program Chair:
Reiner Hartenstein
Kaiserslautern University
Postfach 3049
D-67653 Kaiserslautern - Germany
Phone: +49 631 205 2606
Phone: +49 631 205 2640
mailto:hartenst@rhrk.uni-kl.de

Sunday, 27 August 2000:

• Excursions (optional):
•   to Salzburg (Mozarts birthplace),  fortress Hohensalzburg.
•   to Venice, Italy (2 hours from Villach), or, to
•   Scenic Tour Carinthia

• Registration and Scientific Programme
• Banquet at the Parkhotel

• Scientific Programme
• Boat trip on lake Ossiach with dinner

• Scientific Programme

ELECTRONICS CLUSTER IN CARINTHIA (SILICON ALPS)

Carinthia is known above all as a holiday resort, but Carinthia has more to offer than mountains, lakes and innumerable leisure-time opportunities. In fact only 10% of Carinthias affluence is obtained from tourism. Industry is three times as strong and therefore the most important economic factor. Approximately 350 manufacturing companies employ a work force of around 28,000.
The city of Villach, nestled in the Austrian Alps in Carinthia where Austria, Italy and Slovenia meet, is home to world class high technology companies like Infineon and SEZ, research centres like Carinthia Tech Research and quality educational institutions like the Carinthia Tech Institute, School of Electronics. In recent years the city has taken decisive and innovative steps to further grow its technology base by pursuing an economic development policy designed to create new jobs in the electronics and microelectronics sectors. A major component of this policy is the Micro-Electronic Cluster, a network of technology companies focused in the micro-electronics field as well as their natural partners (suppliers, scientific and educational institutions, and state political organisations) that offer complimentary inputs.

CHARMNG OLD TOWN OF VILLACH

This charming old town with Mediterranean flair surrounded by a vacation area with clear bathing lakes, traditional thermal baths and numerous summer and winter sport resorts is the ideal backdrop for a successful event.
Whether you relax on the Drau river after a hard day's conference or go shopping in the old city centre or just to head for your hotel - everything is right on the doorstep. Hot spring water swimming pools with their health-giving tradition, crystal clear lakes to swim in and hiking in the mountains are just some of the attractive features of this popular holiday region. Take advantage of them on a day out or bring the family with you for a short break.

HOW TO REACH VILLACH.

Villach, Austria's gateway to the south, to both Italy and Slovenia, is a major road and railway junction at which the international lines between Vienna and Venice and between Munich and Ljubljana intersect.
By air: Klagenfurt airport is situated approximately 40 km from Villach. Regular flights from Frankfurt, Zurich and Vienna are operating daily.
By train: Villach is a railway junction and hence easy to reach by train from Munich/Salzburg, Vienna, Innsbruck, Venice and Ljubljana.
By road: Villach can be reached from Germany via the Felbertauern Tunnel or the Tauern Motorway (A10), from Switzerland via Innsbruck and the Felbertauern Tunnel, from Vienna via the Southern Motorway (A2), from Italy via Tarvisio, and from Slovenia via the Wurzen Pass or the Karawanken Motorway (A11).

VILLACH AND CARINTHIA.

Carinthia is the southernmost province of Austria. It extends 9,533 square km; to the south of the main alpine ridge and borders on Slovenia and Italy. 56% of the state lies above an altitude of 1,000 m. The climate is characterised by the Mediterranean influence.