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Sunday, 27.Aug.
Program
Monday, 28 Aug.
Program
Posters
Tuesday, 29 Aug.
Program
Posters
Wednesday, 30 Aug.
Program |
Monday, Aug. 28
|
9:00 - 10:30 Plenum
Session 1
9:00 Welcome and Opening
9:15 Keynote: Tsugio
Makimoto, Hitachi, Tokyo
The Rising Wave of Field-Programmability
10:00 Sriram Govindarajan,
Ranga Vemuri, U Cincinnati
Tightly Integrated Design Space Exploration
with Spatial and Temporal Partitioning in SPARCS |
| 10:30 - 11:00
Coffee Break |
11:00 - 12:40Network
Processors
J.Ditmar, K.Torkelsson, A.Jantsch, Ericsson:
A Dynamically Reconfigurable FPGA-based
Content Addressable Memory for Internet Protocol Characterization
X.Tang, M.Aalsma, Chameleon Systems, Inc.
A Compiler Directed Approach to Hiding
Configuration Loading Latency in Chameleon Reconfigurable Chips
M.Iliopoulos, T.Antonakopoulos, U Patras
Recofigurable Network Processors based
on Field Programmable System Level Integrated Circuits
H.Fallside, M.Smith, Xilinx, Inc.
Internet Connected FPL |
11:00 - 12:40 Prototyping
F.Renner, J.Becker, M.Glesner, U Darmstadt
Field Programmable Communication Emulation
and Optimization for Embedded System Design
H.Krupnova, G.Saucier, INP Grenoble/CSI
FPGA-Based Emulation: Industrial and
Custom Prototyping Solutions
R.Kress, A.Pyttel, A.Sedlmeier, Infineon
Technologies AG
FPGA-based Prototyping for Product
Definition
E.Canto, J.Moreno, J.Cabestany, I.Lacadena,
J.Insenser, TU of Catalunya, Barcelon
Implementation of Virtual Circuits
by Means of the FIPSOC Devices |
|
| 12:40 - 14:00
Lunch Break |
14:00 - 16:05 Dynamically
Reconfigurable I
J.Gause, P.Cheung, W.Luk, IC London
Static and Dynamic Reconfigurable Designs
for a 2D Shape-Adaptive DCT
R.Sidhu, S.Wadhwa, A.Mei, V.Prasanna, USC
A Self-Reconfigurable Gate Array Architecture
H.Simmler, L.Levinson, R.Maenner, U Mannheim
Multitasking on FPGA Coprocessors
M.Vasilko, Bournemouth U
Design Visualisation for Dynamically
Reconfigurable Systems
D.Robinson, P.Lysaght, U Strathclyde
Verification of Dynamically Reconfigurable
Logic |
14:00 - 16:05 Student
Papers
T.Bartzick, M.Henze, J.Kickler, K.Woska,
U Siegen
Design of a Fault-Tolerant FPGA
R.McCready, U Toronto
Real-Time Face Detection on a Configurable
Hardware System
P.Pfeifer, TU Prague
Multifunctional programmable single-board
CAN monitoring module
P.Tomaszewicz, Warsaw U
Self-Testing of Linear Segments in
User-Programmed FPGAs
G. Lías Villar, U Vigo
Implementing a Fieldbus Interface Using
a FPGA |
|
| 16:05 - 16:30 Coffee
Break |
16:30 - 18:35 Technology
Mapping and R&P
S.Krishnamoorthy, S.Swaminathan, R.Tessier,
U Massachusetts
Area-Optimized Technology Mapping for
Hybrid FPGAs
J.Abke, E.Barke, U Hannover
CoMGen: Direct Mapping of Arbitrary
Components into LUT-Based FPGAs
S.Chandra Jain, A.Kumar, S.Kumar, IIT New
Delhi
Efficient Embedding of Partitioned
Circuits onto Multi-FPGA Boards
Anderson, J.Saunders, S.Nag, C.Madabhushi,
R.Jayaraman, Xilinx, Inc.
A Placement Algorithm for FPGA Designs
with Multiple I/O Standards
H.Kropp, C.Reuter, U Hannover
A Mapping Methodology for Code Trees
onto LUT-based FPGAs |
16:30 - 18:35 Biologically
Inspired Methods
J.Torresen, U Oslo
Possibilities and Limitations of Applying
Evolvable Hardware to Real-World Applications
Y.Yamaguchi, A.Miyashita, T.Maruyama,
T.Hoshino, U Tsukuba
A Co-processor System with a Virtex
FPGA for Evolutionary Computation
C.Bauer, P.Zipf, H.Wojtkowiak, U Siegen
System Design with Genetic Algorithms
J.Zhu, G.Milne, U of South Australia,
Adelaide
Implementing Kak Neural Networks on
a Reconfigurable Platform
S.Maya, R.Reynoso, C.Torres, M.Arias-Estrada,
INAOE Puebla - Compact Spiking Neural Network Implementation in FPGA |
|
| 18:35 - 19:30 Break |
| 19:30
Banquet at the Parkhotel |
|
