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Sunday, 27.Aug.
Program
Monday, 28 Aug.
Program
Posters
Tuesday, 29 Aug.
Program
Posters
Wednesday, 30 Aug.
Program |
Wednesday, Aug. 30
|
| 8:30 - 10:30 Plenum
Session 3
8:30 Keynote: Tom
Kean, Algotronix
It‘s FPL, Jim - but not as we know
it!
Market Opportunities for the new Commercial
Architectures
9:15 Invited Paper: Hideharu
Amano, Yuichiro Shibata, Masaki Uno, Keio U, Yokohama
Reconfigurable Systems: New Activities
in Asia
10:00 Oskar
Mencer, Heiko Huebert, Patrick Hung, Martin Morf, Michael J. Flynn, Stanford
U
StReAm: Object-Oriented Programming
of Stream Architectures using PAM-Blox |
| 10:30 - 11:00
Coffee Break |
11:00 - 12:40 Architectures
E.Caspi, M.Chu, R.Huang, J.Yeh, A.DeHon,
J.Wawrzynek, UC Berkeley
Stream Computations Organized for Reconfigurable
Execution(SCORE): Introduction snd Tutorial
H.Lange, A.Koch, TU Braunschweig
Memory Access Schemes for Configurable
Processors
A.Doering, G.Lustig, Medizinische U Luebeck
Generating Adresses for Multi-dimensional
Array Access in FPGA On-chip Memory
A.Derbyshire, W.Luk, IC London
Combining serialisation and Reconfiguration
for FPGA Designs |
11:00 - 12:40 Methodology
and Technology
G.Constantinides, P.Cheung, W.Luk, IC
London
Multiple Resource Binding
M.Vasilko, G.Benyon-Tinker, Bournemouth
U
Automatic Temporal Floorplanning with
Guaranteed Solution Feasibility
K. Aoyama, H. Sawada, A. Nagoya, K.Nakajima,
NTT Laboratories.
A Threshold Logic-based Recofigurable
Element with a Novel Programming Technology
A.Krasniewski, Warsaw U
Exploiting Reconfigurability for Effective
Detection of Delay Faults in LUT-Based FPGAs |
|
| 12:40 - 14:00
Lunch Break |
14:00 - 15:40 Compilation
and Related Issues
A.Takayama, Y.Shibata, K.Iwai, H.Amano,
Keio U
Dataflow Partitioning and Scheduling
Algorithms for WASMII, a Virtual Hardware
B.Kastrup, J.Trum, O.Moreira, J.Hoogerbrugge,
J.v. Meerbergen, Philips Laboratories
Compiling Applications for ConCISe:
An Example of Automatic HW/SW Partitioning and Sythesis
O.Diessel, G.Milne, U o’South Australia,
Adelaide
Behavioral Language Compilation with
Virtual Hardware Management
V.Sklyarov, U Aveiro
Synthesis and Implementation of RAM-based
Finite State Machines in FPGAs |
14:00 - 15:40 Applications
II
S.Ichikawa, H.Saito, L.Udorn, K.Konishi,
Toyohashi U
Evaluation of Accelerator Designs for
Subgraph Isomorphism Problem
M.Edwards, P.Green, UMIST
The Implementation of Sychronous Dataflow
Graphs Using Reconfigurable Hardware
T.Courtney, R.Turner, R.Woods,Queens U
Belfast
A New Coding System for Use with Reconfigurable
Filters
C.Bobda, T.Lehmann, Paderborn U
Efficient Building of Word Recognizer
in FPGAs for Term-Document Matrices Construction |
|
| 15:40 - 16:00 Closing
Session |
|
