_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_| _| _| _| _| _| _|_|_|_| _|_|_|_| _| _| _|_|_|_| _|_|_|_| _| _| _| _| _| _| _| _| _| _| _| _| _| _| _| _| _| _| _| _| _| _| _| _|_|_| _|_|_|_| _| _|_|_|_| _|_|_|_| _| _| _| _| _| _| _| _| _| _| _| _| _| _| _| _| _| _| _| _| _|_|_|_| _|_|_|_| _|_|_|_| _| _| _| _| _| _|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_| F P L '98 E I G H T H I N T E R N A T I O N A L W O R K S H O P FIELD PROGRAMMABLE LOGIC AND APPLICATIONS (http://xputers.informatik.uni-kl.de/FPL/index_fpl.html) Advance Program =============== _|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_| _| _| _| August 31 - September 3, 1998 (Monday - Thursday) _| _| _| _| Tallinn, Estonia _| _| _| _|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_| Aim: From tinkertoy to parallel computing paradigm ==== The methodology of reconfigurable circuits and systems is evolving from tinkertoy approach to an: Innovative Parallel Computing Paradigm which combines computing in time with computing in space. The aim of this workshop is to bring together workers from throughout the world for a wide ranging discussion of all forms of field programmable logic, particularly field programmable gate arrays and complex programmable logic devices, and their applications. It is intended to discuss the increasing range of device types, industrial applications, advanced design tool development, research applications, novel system architectures and educational experiences. The workshop will include regular presentations, posters and discussion sessions, and it is expected that most of the delegates will wish to make some contribution to one or more of these. The workshop is the eighth in a series of workshops which were held in Oxford (1991, 1993 and 1995), Vienna (1992), Prague (1994), Darmstadt (1996) and London (1997). The following program is subject to change without notification. ==================================================================== Sunday, Aug. 30 ==================================================================== -------------------------------------------------------------------- 20.00 Informal Gathering and Registration at the Hotel Viru (lobby) -------------------------------------------------------------------- ==================================================================== Monday, Aug. 31 ==================================================================== -------------------------------------------------------------------- 8.00 - 9.00 Registration at Tallinn National Library -------------------------------------------------------------------- 9.00 - 9.20 Opening Session -------------------------------------------------------------------- 9.20 - 10.20 Keynote -------------------------------------------------------------------- V.Milutinovic, University of Belgrade: Key Issues in Reconfigurable Computing -------------------------------------------------------------------- 10.20 - 10.35 Coffee Break -------------------------------------------------------------------- 10.35 - 12.15 Session 1: Design Methods -------------------------------------------------------------------- D.Robinson, P.Lysaght, G.McGregor, U Strathclyde: New CAD Framework Extends Simulation of Dynamically Reconfigurable Logic W.Luk, S.McKeever, IC London: Pebble: A Language For Parametrised and Reconfigurable Hardware Design V.Sklyarov, R.Sal Monteiro, N.Lau, A.Melo, A.Oliveira, K.Kondratjuk, Aveiro U: Integrated Development Environment for Logic Synthesis of Digital Circuits Based on Dynamically Reconfigurable FPGAs R.Hartenstein, M.Herz, F.Gilbert, U Kaiserslautern: Designing for the Xilinx XC6200 FPGAs -------------------------------------------------------------------- 12.15 - 13.30 Lunch -------------------------------------------------------------------- 13.30 - 15.10 Session 2: General Aspects -------------------------------------------------------------------- J.Becker, A.Kirschbaum, F.-M.Renner, M.Glesner, TU Darmstadt: Perspectives of Reconfigurable Computing in Research, Industry and Education G.Brebner, U Edinburgh: Field-Progammable Logic: Catalyst for New Computing Paradigms W.Luk, NShirazi, P.Y.K.Cheung, IC London: Run-time management of partially-reconfigurable designs M.Platzner, G.De Micheli, Stanford U: Acceleration of Satisfiability Algorithms by Reconfigurable Hardware -------------------------------------------------------------------- 15.10 - 15.30 Coffee Break -------------------------------------------------------------------- 15.30 - 17.10 Session 3: Prototyping / Simulation -------------------------------------------------------------------- J.Stohmann, K.Harbich, M.Olbrich, E.Barke, U Hannover: An Optimized Design Flow for Fast FPGA-Based Rapid Prototyping H.Krupnova, G.Saucier, INP Grenoble: A Knowledge-Based System for Prototyping on FPGAs R.Macketanz, W.Karl, TU Munich: JVX - A Rapid Prototyping System Based on Java and FPGAs J.Shetler, B.Hemme, C.Yang, C.Hinsz, Cal Poly: Prototyping New ILP Architectures Using FPGAs -------------------------------------------------------------------- 18.30 Reception at Tallinn Town Hall -------------------------------------------------------------------- ==================================================================== Tuesday, Sep. 1 ==================================================================== -------------------------------------------------------------------- 8.30 - 10.10 Session 4: Development Methods -------------------------------------------------------------------- Samary Baranov, Ben Gurion U Negev: CAD System for ASM and FSM Synthesis J.M.Emmert, A.Randhar, D.Bhatia, U Cincinnati: Fast Floorplanning for FPGAs M.Renovell, J.M.Portal, J.Figueras, Y.Zorian, LIRMM-UM2: SRAM-Based FPGAs: A Fault Model for the Configurable Logic Modules G.Haug, W.Rosenstiel, FZI Karlsruhe: Reconfigurable Hardware as Shared Resource in Multipurpose Computers -------------------------------------------------------------------- 10.10 - 10.35 Coffee Break -------------------------------------------------------------------- 10.35 - 11.50 Session 5: Accelerators -------------------------------------------------------------------- S.Robinson, M.Caffrey, M.Dunham, LANL Reconfigurable Computer Array: The Bridge Between High Speed Sensors and Low Speed Computing W.Luk, P.Andreou, N.Shirazi, D.Siganos, IC London: A Reconfigurable Engine for Real-Time Video Processing F.-M.Renner, J.Becker, M.Glesner, TU Darmstadt: An FPGA Implementation of a Magnetic Bearing Controller for Mechatronic Applications -------------------------------------------------------------------- 11.50 - 13.05 Session 6: System Architectures -------------------------------------------------------------------- R.Hartenstein, M.Herz, T.Hoffmann, U.Nageldinger, U Kaiserslautern: Exploiting contemporary memory techniques in reconfigurable accelerators A.Donlin, U Edinburgh: Self Modifying Circuitry - A Platform for Tractable Virtual Circuitry K. GajjalaPurna, K.Simha, D.Bhatia, U Cincinnati: REACT: Reactive Environment for Runtime Reconfiguration -------------------------------------------------------------------- 13.05 - 14.20 Lunch -------------------------------------------------------------------- 14.20 - 16.00 Session 7: Applications -------------------------------------------------------------------- S.Charlwood, P.James-Roxby, U Birmingham: Evaluation of the XC6200-series architecture for cryptographic applications A.Zakerolhosseini, P.Lee, E.Horne, U Kent: An FPGA based object recognition machine G.Acher, W.Karl, M.Leberecht, TU Munich: PCI-SCI Protocol Translations: Applying Microprogramming Concepts to FPGAs T.Callahan, J.Wawrzynek, UC Berkeley Instruction-Level Parallelism for Reconfigurable Computing -------------------------------------------------------------------- 14.20 - 15.35 Session 8: Poster Introduction (parallel to S.7) -------------------------------------------------------------------- 15.35 - 16.20 Poster Exhibition (partially par. to S.7) -------------------------------------------------------------------- N.L.Miller, S.F.Quigley, U Birmingham: A Novel Field Programmable Gate Array Architecture for high speed arithmetic processing D.MacVicar, S.Singh, XILINX: Accelerating DTP with Reconfigurable Computing Engines C.N.Ojeda-Guerra, R.Esper-Chain, M.Estupinan, A.Suarez, U Las Palmas: Hardware Mapping of a Parallel Algorithm for Matrix-Vector Multiplication G.Brebner, U Edinburgh: An Interactive Datasheet for the Xilinx XC6200 N.Woolfries, P.Lysaght, S.Marshall, G.McGregor, D.Robinson, U Strathclyde: Fast Adaptive Image Processing in FPGAs using Stack Filters S.Sawitzki, A.Gratz, R.Spallek, U Dresden: Increasing Microprocessor Performance with Tightly-Coupled Reconfigurable Logic Arrays N.Bergmann, P.Sutton, Queensland U: A High-Performance Computing Module for a Low Earth Orbit Satellite using Reconfigurable Logic S.Yamagiwa, M.Ono, T.Yamazaki, P.Kulkasem, M.Hirota, K.Wada, U Tsukuba: Maestro-Link: A High Performance Interconnect for PC Cluster T.Shiozawa, K.Oguri, K.Nagami, H.Ito, R.Konishi, N.Imlig, NTT: A Hardware Implementation of Constraint Satisfaction Problem Based on New Reconfigurable LSI Architecture P.Merino, J.Lopez, M.Jacome, U Politecnica de Madrid: A Hardware Operating System for Dynamic Reconfiguration of FPGAs E.Cerro-Prada, P.B.James-Roxby, U Birmingham: High speed low level image processing on FPGAs using distributed arithmetic T.-T.Do, H.Kropp, C.Reuter, P.Pirsch, U Hannover: A Flexible Implementation of High-Performance FIR Filters on Xilinx FPGAs I.Vassanyi, U Veszprem: Implementing processor arrays on FPGAs S.Holmstrom, K.Sere, Abo Akademi U: Reconfigurable Hardware - A Study in Codesign C.Ackad, TU Braunschweig: Statechart-based HW/SW-Codesign of a Multi-FPGA-Board and a Microprocessor -------------------------------------------------------------------- 16.20 - 16.40 Coffee Break -------------------------------------------------------------------- 16.40 - 18.00 Session 9: Hardware/Software Codesign -------------------------------------------------------------------- G.McGregor, D.Robinson, P.Lysaght, U Strathclyde: A Hardware/Software Co-design Environment for Reconfigurable Logic Systems K.Bondalapati, V.Prasanna, U of Southern California: Mapping Loops onto Reconfigurable Architectures S.Asaad, K.Warren, IBM T.J.Watson Research Center: Speed Optimization of the ALR circuit using an FPGA with embedded RAM: A Design Experience -------------------------------------------------------------------- 19.30 Banquet at von Glehn's castle -------------------------------------------------------------------- ==================================================================== Wednesday, Sep. 2 ==================================================================== -------------------------------------------------------------------- 8.30 - 9.45 Session 10: System Development -------------------------------------------------------------------- R.Kress, A.Pyttel, A.Sedlmeier, Siemens AG: High-level Synthesis for Dynamically Reconfigurable HW/SW-Systems N.McKay, S.Singh, XILINX: Dynamic Specialisation of XC6200 FPGAs by Partial Evaluation S.Guccione, XILINX: Webscope: A Circuit Debug Tool -------------------------------------------------------------------- 9.45 - 10.00 Coffee Break -------------------------------------------------------------------- 10.00 - 11.40 Session 11: Algorithms on FPGAs -------------------------------------------------------------------- D.Lavenier, Y.Saouter, IRISA-CNRS: Computing Goldbach partitions using pseudo-random bit generator operators on a FPGA systolic array P.Zhong, M.Martonosi, S.Malik, P.Ashar, Princeton U: Solving Boolean Satisfiability with Dynamic Hardware Configurations J.Põldre, M.Mandre, K.Tammemäe, Tallinn Technical U: Modular exponentiator realization on FPGA B.Feher, G.Szedo, TU Budapest: Cost effective 2x2 inner product processors -------------------------------------------------------------------- 10.00 - 11.15 Session 12: Poster Introduction (parallel to S.11) -------------------------------------------------------------------- 11.15 - 12.00 Poster Exhibition (partially par. to S.11) -------------------------------------------------------------------- A.Touhafi, W.F.Brissinck, E.F.Dirkx, U Brussel: Simulation of ATM switches using Dynamically Reconfigurable FPGA's T.Rissa, T.Mäkeläinen, J.Siirtola, J.Niittylahti, Tampere U: Fast Prototyping Using System Emulators A.Dandalis, V.Prasanna, U of Southern California: Space-efficient Mapping of 2D-DCT onto Dynamically Configurable Coarse-Grained Architectures I.Lemberski, M.Ratniece, Riga Aviation U: XILINX4000 Architecture-Driven Synthesis for Speed V.Tomachev, Inst. of Eng. Cybernetics Belarus: The PAL-implementation of Boolean function characterized by minimum delay A.Abo Shosha, P.Reinhart, F.Rongen, Research Centre Jülich: Reconfigurable PCI-Bus Interface (RPCI) A.Trost, A.Zemva, B.Zajc, U Ljubljana: Programmable Prototyping System for Image Processing J.Fischer, C.Mueller, H.Kurz, TU Aachen: A Co-Simulation Concept for an Efficient Analysis of Complex Logic Designs A.Döring, W.Obelöer, G.Lustig, Med. U Lübeck: Programming and Implementation of Reconfigurable Routers M.Moure, U Vigo: Virtual Instruments based on reconfigurable logic C.Siemers, D.Moeller, FH Westkueste: The >S