Theme and Scope

Theme

On the eve of the third millennium...

...a time for review and for considering the future of programmable logic
  FPL’99 is likely to be the last major workshop on Field Programmable Logic before the new millennium. It presents the participants with an opportunity to review the work of the last decade and to look forward to what we can expect in the coming decade. The most obvious changes relate to device size and speed, where device capacities exceeding one million gates and speeds of 1GHz are technically feasible now. The biggest challenges are arguably in the domain of software and design tools in general. Areas such as intellectual property cores, system-on-chip design, and reconfigurable systems technology, in all its forms, will undoubtedly become more significant in the future.
   

Scope
  • Novel device, machine and system architectures
  • New software and hardware development tools
  • Reconfigurable and partially reconfigurable designs
  • Dynamically reconfigurable logic and systems
  • High-level design and compilation research
  • Industrial applications and experiences
  • Trade-offs between devices, architectures and technologies
  • Reconfigurable custom computing machines
  • Hardware/software co-design for field programmable logic
  • Microprocessor/FPGA hybrid devices
  • ASIC emulators, hardware modellers and compiled accelerators
  • Fault modelling, testability methods and reliability issues
  • Educational experiences and opportunities
  • Reconfigurable accelerators and their applications
  • Speed-up effects - survey and analysis
  • Testing of reconfigurable circuits
  • Benchmarking and profiling
  • Applications from a wide variety of areas
  • Evolvable and adaptable systems

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 Last Modified : 30/03/99. Suggestions or Comments to FPL99@eee.strath.ac.uk