KARL-related Quotation Index
[ KARL user list | The History of KARL and ABL ]

(Literature from authors outside Kaiserslautern on KARL, ABL, CVS_BK and its Applications, or, referencing such Literature from Kaiserslautern)

quotations followed up til 1992 - last modification 1997

  1. P. Haselmeier: The KARL language compiler; report no. 77-14; Instituto di Elettronica, Politechnco di Milano, Milano, Italy, 1977
  2. P. A. Anderson, M. Nygaard: A study of different languages for description and simulation of digitalsystems; report no. 6/78. Univ. Trondheim, CS Division, Trondheim, Norway, 1978
  3. H. Hedengran: A Parser for KARL 2, internal report; Dept. of Applied Electronics, The Royal Inst. of Technology, Stockholm, Sweden, 1980
  4. M. Breuer, R. Hartenstein: Computer Hardware Description Languages and their Applications; North Holland, Amsterdam/New York, 1981
  5. G. Girardi: ABL editor: cell definition CVT-report; CSELT, Torino, Italy; Jan. 1984
  6. G. Girardi: ABL data structure; CVT-report; CSELT, Torino, Italy, March 1984
  7. G. Girardi: ABL editor: user manual (draft); CSELT, Torino, Italy, July 1984
  8. H. Bäßmann: Architektur und Mikroprogrammierung von Rechnersystemen mit Hilfe der Register-Transfer-Sprache KARL-II; Diplom-arbeit; Universität Bremen, 1984
  9. M. Bedina, F. Distante: On SW development of a Petri Net model for VLSI functional test, CVT report, Politecnico di Milano, Italy, 1984
  10. F. Ferrara, G.Rosenga: Translation of RT Hardware Description into Propositional Logic Representation, CVT rep; CSELT, Torino, 1984
  11. P. G. Bosco, G. Giandonato, E. Giovanetti: Verification of Hardware Descriptions against Temporal Logic Specifications; CVT report; CSELT, Torino, Italy, 1984
  12. C.Segre, S. Morpurgo: Proposed Algorithm for a Testability Analysis Tool based on KARL (CVTOTAKA); CVT report, Ing.Olivetti S.p.A.,Ivrea,Italy, 1984
  13. C.Segre, S. Morpurgo: Olivetti Fault Simulator For RT-Level (KARL) Described Nets; CVT report, Ing.Olivetti S.p.A.,Ivrea,Italy, 1984
  14. C.Segre, S. Morpurgo: Olivetti's Fault Generator For RT-Level (KARL) Described Nets (CVTOFGKA): User manual; CVT report, Ing.Olivetti S.p.A.,Ivrea,Italy, 1984
  15. C.Segre, S. Morpurgo: Olivetti's Fault Simulator For RT-Level (KARL) Described Nets (CVTOFSKA): User manual; CVT report, Ing.Olivetti S.p.A.,Ivrea,Italy, 1984
  16. G. Girardi: CVT-KARENE System-ABLED: Graphic Editor at Register Transfer Level; CVT report; CSELT, Torino, Italy, 1984
  17. N. N.: Specification of the CVT KARENE System; IMAG, Grenoble, 1984
  18. S. Marine, G. Girardi, A. Zappalorto: Draft proposal for the final definition of mixing behaviour and structure in CVT KARENE system; CVT report; IMAG, Grenoble, France / CSELT, Torino, Italy, 1984
  19. W. Graß, N. Schielow: Automatische Verifikation logischer Entwürfe; Informatik-Fachberichte 84; Springer-Verlag, 1984, p.113-126
  20. M. Melgara, M. Paolini, R. Roncella, S. Morpurgo:CVT-FERT: Automatic generator of analytical faults at RT level from electrical and topological descriptions; Int'l Test Conf., Philadelphia, USA, 1984
  21. N.N.: CVT-TIGER: Algorithms and Tool Description; CSELT, Torino, Italy, 1985
  22. C.Segre, S. Morpurgo: The Olivetti Fault Simulator For RT-Level (KARL) Described Nets: User's Manual; CVT report, Ing.Olivetti S.p.A.,Ivrea,Italy, 1985
  23. C.Segre, S. Morpurgo: The Olivetti Fault Generator For RT-Level (KARL) Described Nets (CVTOFGKA): User's  Manual; CVT report, Ing.Olivetti S.p.A.,Ivrea,Italy, 1985
  24. A.Pawlak: A Tutorial Guide to Modern Hardware Description and Design Languages; EUROMICRO Symposium, Brussels, Belgium, 1985
  25. G. Girardi, R. Hartenstein, U. Welters: ABLED - a RT Level Schematic Editor and Simulator User Interface; CVT rep, Kaiserslautern, 1985
  26. S. Morpurgo, A. Hunger, M. Melgara, C. Segre: RTL Validation of VLSI: An Integrated Set of Tools for KARL; IFIP Int'l Symposium on Computer Hardware Description Languages, (CHDL'85); Tokyo, Japan, 1985
  27. W. Grass, N. Schielow: Verena: A Program for automatic verifications of the register transfer description; IFIP Int`l Symp. CHDL`85; Tokyo, Japan, 1985
  28. N.N.: CVT fault generator and simulator level on KARL description nets; CVT report, Ing. Olivetti S.p.A., Ivrea, Italy, 1985
  29. G. Girardi, A. Zappalorto: An experiment on designing with KARENE; the behavioural level; CVT report, CSELT, Torino, Italy, 1985
  30. I. Stamelos, M. Melgara: CVT TIGER: a RT-level Test Pattern Generation and Validation Environment; report, CSELT/Univ. of Thessaloniki/Olivetti, Torino, Italy, 1985
  31. S. Morpurgo, C. Segre: Fault Simulation, at Register Transfer Level, of VLSI; Olivetti Research and Technology Review 3, 1985
  32. P. Prinetto, M. Siviero, V. Vercellone: Progretto di un sistema di elaborazione microprogrammabile: BENC83; Politecnico di Torino, Torino, Italy, 1985
  33. P. Prinetto, M. Siviero: Descrizione e simulazione in ART* e KARL II del multiplicatore TRW MPY 24-MJ; Politecnico di Torino, Torino, Italy, 1985
  34. P. Prinetto, M. Siviero: Analisi comparata dei sistemi di simulazione ART* e KARL II; Politecnico di Torino, Torino, Italy, 1985
  35. Grass,W., Rauscher, R.: A Practicable Strategy for the Verification of Interactive Microprogram Transformations, EUROMICRO 1085, Brussels, Belgium, North Holland, 1985
  36. M. Rauscher, W. Grass: Experiences in Using KARL in PRIMITIVE (Program for Interactive Microprogram Transformation and its Verification); ABAKUS workshop; Passau, 1986
  37. M. Schielow, W. Grass: KARL Use in VERENA (Verification of RT Structures); ABAKUS workshop; Passau, 1986
  38. G. Girardi, U. Welters: A Graphic RT-level Editor based on the KARL Compiler Interface; ABAKUS workshop; Passau, Germany, 1986
  39. M. Melgara: A User-Assisted Test Pattern Generator and Validation Environment based on KARL; ABAKUS workshop; Passau, 1986
  40. D. Farelly: The Practical Application of ABLED and KARL in Designing a Speech Synthesizer; ABAKUS workshop; Passau 1986
  41. C. Whiting The CVS Logic Optimizer; ESPRIT Project Discussion Paper; British Telecom, Ipswich, UK, June 1986
  42. G. P. Balboni, V. Vercellone: Experiences in Using KARL-III in Designing a CMOS Circuit for Packet-Switched Networks; ABAKUS workshop; Passau, Germany, 1986
  43. L. Lavagno, R. Munione: Automatic Layout Generation from (KARL) RT Level Descriptions; ABAKUS workshop; Passau, 1986
  44. S. Marine: IRENE un Langage pour la description, simulation et synthèse automatique du matériel VLSI; diss., INPG, Grenoble, 1986
  45. N.N.: CVT software catalogue; CSELT, Torino, Italy, 1986
  46. G.Arato, R. Manione: PSICO: a System for Automatic Layout Synthesis; CSELT, Torino, 1986
  47. I. Stamelos, M. Melgara, M. Paolini, S. Morpurgo, C. Segre: A Multi-Level Test Pattern Generation and Validation Environment; International Test Conference, 1986
  48. Rauscher, R.: Ein praktikables Verfahren zur interaktiven Mikroprogrammtrans- formation und deren automatischer formaler Verifikation, Dissertation, Universität Hamburg, 1986
  49. A. Butterfield: From KARL to CIF - Automatic Conversion of High-Level RT Descriptions to an Equivalent High-Level Layout Description; internal report, CS Dept.,Trinity College, Dublin, Ire, 1986
  50. D. McCarthy: KARL as a Laboratory Instrument in Tertiary Computer Science Courses; internal report, CS Dept.,Trinity College, Dublin, Ire 1986
  51. Ph. Besslich, H. Bäßmann: Benutzer-Handbuch für die Register-Transfer-Sprache KARL-II; Ber. FB-1, WE "Theoretische Elektrotechnik und Digitale Systeme", Fachgeb. Digitaltechnik und Schaltwerksentwurf; Univ. Bremem, 1986
  52. N. N.: ABAKUS workshop Passau, Germany, June 17 - 20, 1986 - Collection of Viewgraphs; Passau / Kaiserslautern, August 1986
  53. G. Girardi, R. Hartenstein: ABLED - ein CAD-Werkzeug f. den Entwurf von Digitalsystemen; DECUS München Symposium, Stuttgart 1986
  54. W. Graß, R. Rauscher: CAMILOD - A Program System for Designing Digital Hardware with Proven Correctness; in (ed. D. Borrione): Proc IFIP Workg Conf. "From HDL Descriptions to Guaranteed Correct Circuit Designs"; Grenoble, France, Sept 1986
  55. A. Pepe: The Verification of Temporal Properties in RTL Descriptions: an Experimental System; internal rep; CSELT, Torino, Italy, 1986
  56. L. Lavagno, R. Manione: Register Transfer to Layout Synthesis using enhanced Standard / Macro Cell Architecture; internal report; CSELT, Torino, Italy, 1986
  57. I. Stamelos, M. Melgara, M. Paolini, S. Morpurgo, C. Segre: A Multi-Level Test Pattern Generation and Validation Environment; Int'l Test Conf. 1986
  58. H. Bässmann, Ph. Besslich: Ein Mikroassembler für die Register-Transfer-Sprache KARL-II; Bericht 1/86; F.B. Elektrotechnik, Un. Bremen, 1986
  59. Ph. Besslich, H. Bässmann: Simulation mikroprogrammierbarer Hardwarestrukturen mit der RTL KARL-II; Bericht No. 2/86; F.B. Elektrotechnik, Universität Bremen, 1986
  60. N.N.: Monitor User's Manual; CVT report, CSELT, Torino, Italy, 1986
  61. N.N.: Testing Tools for RT level (KARL) described nets: User Manual; CVT rep.; Olivetti, Ivrea, Italy, 1986
  62. N.N.: Olivetti testability analysis tools based on KARL; CVT rep.; Olivetti, Ivrea, Italy, 1986
  63. N. N.: Validation tools at different levels and combined testing: final report; CVT report, RWTH Aachen, 1986
  64. F. R. Wagner, C. M. Freitas,L. G. Colendziner: Equivalencia de Descrições Textuais de Gráficas de Sistemas Digitais num Anbiente de CAD; Seminario Integrado de Software a Hardware XIII, Recife, PE (Brazil), July 1986, Anais, UFPe, 1986, p. 486-493
  65. F. R. Wagner, C. M. Freitas, L. G. Colendziner, F. M. Oliveira, L. F. R. Machado: Modelagem Automatizada a Nível RT de Circuito; SeminarioIntegrado de Software a Hardware XIII, Recife, PE (Brazil), July 1986, Anais, UFPe, 1986
  66. F. R. Wagner, C. M. Freitas, L. G. Colendziner, F. M. Oliveira, L. F. R. Machado:, Metodologia de Projeto de Sistemas Digitais num Ambientede CAD; Seminario Integrado de Software a Hardware XIV, Salvador, BA(Brazil), 1987, Anais, UFPe, 1986, p. 131-141
  67. Buschke, W. Grass, W. Rauscher, R.: BOSS - A Functional Block Oriented Intermediate Language for RT-Level Hardware Descriptions; EUROMICRO 1986, Venice, Italy, September 1986, in:: Microprocessing and Microprogramming, North Holland, Amsterdam, 1986
  68. A. Butterfield, D. P. McCarthy: Teaching the Use of KARL for Customer / Supplier Interface Applications; Proc. European Conference on Customer/Vendor Interfaces in Microelectronics, Kaiserslautern, Sept 23/24 1986; GMD Lecture Notes, St. Augustin, 1987
  69. N. Schielow: (title to be inserted here), Diplomarbeit, Fachbereich Informatik, Universität Hamburg, 1987
  70. A. Bonomo, G. Bussolino, G. Girardi, M. Italiano: From Structured RT Description to Floor-Plan; internal report; CSELT, Torino, Italy, 1986 - also: EUROMICRO Symposium, Portsmouth, UK, 1987
  71. L. Lavagno, R. Manione: SMART, SiMulator At Register Transfer level; internal report, CSELT, Torino, Italy, 1987
  72. L. Lavagno, R. Manione: From Register Transfer to Silicon via Enhanced Standard /MacroCell Architecture; rep, CSELT, Torino Italy 1987
  73. A. Bonomo, G. Girardi, L. Lavagno, R. Hartenstein, R. Hauck: . Syntax Diagrams of the CVS_BK Language (CVS Behavioural Karl); ESPRIT / CVS report, CSELT, Torino, Italy / Informatics Dept., Univ. Kaiserslautern 1987
  74. A. Bonomo, G. Girardi, L. Lavagno, R. Hartenstein, R. Hauck: Semantic Specification of CVS_BK Language (CVS Behavioural Karl); ESPRIT / CVS report, CSELT, Torino, Italy /Informatics Dept., Univ. Kaiserslautern, 1987
  75. F. R. Wagner et al.: A Digital System Design Methodology Based on Nets of Agents; Proc. IFIP CHDL'87 - Symp. on Computer Hardware Description Languages and their Applications; North Holland, Amsterdam, 1987
  76. K. Haimann: Entwurf und Simulation mikroprogrammierter Rechner mit der Hardwarebeschreibungssprache KARL-III; Diplomarbeit Nr. 513, Informatik, Universitaet Stuttgart, Nov. 1987
  77. F. R. Wagner, C. M. Freitas, L.G. Colendziner, F.M. Oliveira, L. F. R. Machado: Linguagens de Descrição do Processo de Projeto em AMPLO; Porto Allegre, RGS (Brazil), CPGCC- URGS, March 1987, 17 p., Relatorio de Pesquisa 66 (research report no. 66)
  78. N.N.: Efficiency of validation tools at different levels; CVT report, RWTH Aachen, 1985
  79. A. Pawlak: HL Design Tools - The E.I.S. Perspective; E.I.S. Workshop, GMD Schloß Birlinghoven, Oct. 1987
  80. A. Pawlak: Report on the CHDL'87 Conference - Amsterdam, April 27 - 29, 1987; E.I.S. Workshop, GMD Schloß Birlinghoven, Oct. 1987
  81. A. Pawlak: Lecture Notes on Hardware Description Languages - Lecture Notes; Arbeitspapiere der GMD, No. 255, GMD Schloß Birlinghoven, July 1987
  82. F. R. Wagner, C. M. Freitas,L. G. Colendziner: The AMPLO System: An Integrated Environment for Digital System Design; IFIP Workshop on Tool Integration and Design Environments; Paderborn, Germany, Nov. 1987, North Holland , Amsterdam, 1987
  83. F. R. Wagner: KAPA - Una Linguagem para e Descrição de Hardware no Nivel de Transferencia entre Registrados; Porto Allegre, RGS (Brazil), CPGCC - UGermanyS, April 1987, 40 p., Relatorio de Pesquisa 68 (research rep. no. 68)
  84. C. M. Dal Sasso-Freitas, F. R. Wagner, F. M. Oliveira: Especificação do Editor Grafico KAPA; Porto Allegre, RGS Brazil), CPGCC UGermanyS, April 1987, 62 p., Relatorio de Pesquisa 68 (research rep. no. 62)
  85. R. Rauscher, J. Westendorf: A System for Verification of Interactive Microprogram Transformations; EUROMICRO Symposium, Ports-mouth, UK, Sept, 1987
  86. K. Haimann: Entwurf und Simulation mikroprogrammierter Rechner mit der Hardware- Beschreibungssprache KARL-3; Diplomarbeit, Institut für Informatik, Univ. Stuttgart, 1987
  87. T. Ohtsuki (Series Editor): Advances in CAD for VLSI; North Holland Publishing Co. New York, Amsterdam, Oxford, Tokyo, 1987
  88. W. Fichtner, M. Morf: VLSI CAD Tools and Applications; Kluwer, Boston, 1987
  89. Rauscher, R. Westendorf, J.: A System for Verification of Interactive Microprogram Transformations; EUROMICRO 1987, Portsmouth, UK, in: Microprocessing and Microprogramming, North Holland, Amsterdam, 1987
  90. Rauscher, R.:Benutzerhandbuch und Dolumentation zu PRIMITIVE. Mitteilung 151 des Fachbereich Informatik, Universität Hamburg, 1987
  91. A. Hunger, M. Melgara, S. Morpurgo, C. Segre: Register Transfer level validation of VLSI; CSELT Technical reports, vol 14, no. 1, Torino, Italy, Febr. 1988
  92. A. Pawlak: Standards in design automation versus KARL/ABL design environment (Invited Paper); Proc. 2nd ABAKUS workshop, Innsbruck, Austria, Sept. 1988
  93. W. Grass: VERENA - A.CAD-tool.for.designing guaranteed.correct.logic.circuits;Proc.2nd ABA-KUS workshop, Innsbruck, Austria, Sept.

    94.      1988
  94. M. Mutz: Logic Verification based on function graphs; Proc. 2nd ABAKUS workshop, Innsbruck, Austria, Sept. 1988
  95. K. Jansen: Transformations of RT-descriptions guided by features of logic implementations to be verified; Proc. 2nd ABAKUS workshop, Innsbruck, Austria, Sept. 1988
  96. A. Bonomo, M. Italiano, L. Lavagno, L. Maggiuli, M. Melgara, M. Paolini, I. Stamelos: Easily testable data part synthesis in the BACH silicon compiler; Proc. 2nd ABAKUS workshop, Innsbruck, Austria, Sept. 1988
  97. A. Bonomo, L. Lavagno, L.: Control part synthesis in the BACH silicon compiler; Proc. 2nd ABAKUS workshop, Innsbruck, Austr Sep 1988
  98. A. Bonomo, G. Girardi, A. Lecce, L. Maggiulli: GENMON: a specialized ABL editor for design methodology descriptions; Proc.2nd ABA-KUS workshop, Innsbruck, Austria, Sept. 1988
  99. S. Rust: An experimental system design environment for chip design; Proc. 2nd ABAKUS workshop, Innsbruck, Austria, Sept. 1988
  100. D. Maertens: Special Problems of the event driven simulation stragtegy; Proc. 2nd ABAKUS workshop, Innsbruck, Austria, 1988
  101. Rauscher, R.: Analysis of design methodologies for digital systems; Proc. 2nd ABAKUS workshop, Innsbruck, Austria, Sept. 1988
  102. A. Jaime, E. Villar: SECUENTEST: Automatic generation of checking experiments for sequential machines; Proc. 2nd ABAKUS workshop, Innsbruck, Austria, Sept. 1988
  103. Cecinati, R., Fossati, R., Licciardi, L., Pacchiotti, A., Paolini, M.: The use of KARL III in the RIPAC chip design; Proc. 2nd ABAKUS workshop, Innsbruck, Austria, Sept. 1988
  104. Donati,N.,Fatini,N.: Experience on CVS-BK use on a signal processor circuit; Proc. 2nd ABAKUS workshop, Innsbruck, Austria,1988
  105. A. Bonomo, M. Italiano, L. Lavagno, L. Maggiuli, M. Melgara, M. Paolini, I. Stamelos: BACH (Behavioural-Level Automated Compilation of Hardware): An Integrated ASIC Synthesis System; ESPRIT Technical Week, Brussels, Belgium 1988
  106. J. Darringer, F. J. Rammig: Computer Hardware Description Languages and their Applications; North Holland, Amsterdam, 1990
  107. A. Balboni, V. Rampa, S. Ravaglia: Comparative Evaluation of Automatic vs. manual Design for an Application-specific DSP; ESPRIIT Conference, Nov.1991, Brussels, Belgium
  108. G. Roos, E. Bernath, T. Büchner, S. Rust, T. Schwederski: Dedicated VLSI Processors for Image Processing; GME-Conference on VLSI; Baden-Baden 1991; VDE-Verlag, Berlin, 1991
  109. V. G. Moshnyaga, H. Onodera, K. Tamaru, H. Yasuura: A Language for Designing Data-Path Module Generators; Int’l Design Workshop "Russian Workshop’92", Moscow, Russia
  110. V. G. Moshnyaga, H. Yasuura: A Data-Path Modules Design from Algorithmic Representations; IFIP WG 10.5 Workshop on Synthesis, Generation and Portability of Library Blocks for ASIC Design, Grenoble, France, Mar 1992
  111. V. G. Moshnyaga, H. Yasuura: A Language for Designing Module Generators; Proc. SASIMI’92 - Synthesis and Simulation Meeting and Int’l Exchange, Kobe, Japan, Apr. 1992
  112. Kees G. W. Goossens: Embedding Hardware Description Languages in Proof Systems; Doctor of Philosophy (Ph. D. thesis) , University of Edinburgh, 1992
  113. M. Vieillot: Mise en oeuvre de l'opérateur Gamma à l'aide de circuits logiques reconfigurables; Thèse, Présentée devant l'Université de Rennes 1, Institut de Formation Supérieure en Informatique et Communication, Pour obtenir Le Titre de Docteur de l'Université de Rennes 1, Mention Informatique, le 2 février 1996
  114. P. Le Moënner: Contribution à la réalisation d'une chaîne complète pour la synthèse de circuits réguliers; Thèse, Présentée devant l'Université de Rennes 1, pour obtenir le grade de : Docteur de l'Université de Rennes 1, Mention Informatique École Doctorale: Sciences Pour l'Ingénieur, le 21 novembre 1997
quotations followed up til 1992 - last modification 1997



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