Reiner W. Hartenstein, Jürgen Becker, et al.: Custom Computing Machines vs. Hardware/Software Co-Design: from a globalized point of view; 6th International Workshop On Field Programmable Logic And Applications, FPL'96, Darmstadt, Germany, September 23-25, 1996, Lecture Notes in Computer Science, Springer Press, 1996  
  Reiner W. Hartenstein, Jürgen Becker, Michael Herz, et al.: A Synthesis System for Bus-based Wavefront Array Architectures; Proceedings of ASAP 96 Application Specific Array Processors, Chicago, USA, August 1996  
  Reiner W. Hartenstein, Jürgen Becker, et al.: High-Performance Computing Using a Reconfigurable Accelerator; CPE Journal, Special Issue of Concurrency: Practice and Experience, John Wiley & Sons Ltd., 1996 
  Reiner W. Hartenstein, Jürgen Becker, et al.: A Novel Machine Paradigm to Accelerate Scientific Computing; Special issue on Scientific Computing of Computer Science and Informatics Journal, Computer Society of India, 1996 
  Reiner W. Hartenstein, Jürgen Becker, et al.: A Novel Hardware/Software Co-Design Framework; Journal of the Brazilian Computer Society: Special Issue on Electronic Design Automation, no.2, vol. 2, pp. 16-26, November 1995 
  Reiner W. Hartenstein: Hardware/Software Co-Design; aktuelles Schlagwort; GI Informatik-Spektrum 18: p.286-287, Springer-Verlag, Oktober 1995 
  Reiner W. Hartenstein: Custom Computing Machines; aktuelles Schlagwort; GI Informatik-Spektrum 18: p.228-229, Springer-Verlag, Oktober 1995 
  A. Ast, J. Becker, R. W. Hartenstein, et al.: Data-procedural Languages for FPL-based Machines; 4rd Int. Workshop On Field Programmable Logic And Applications, FPL'94, Prague, September 7-10, 1994, Lecture Notes in Computer Science, Springer, 1994 
  R. W. Hartenstein, et al.: A New FPGA Architecture for Word-oriented Datapaths; 4th Int. Workshop On Field Programmable Logic And Applications, FPL'94, Prague, September 7-10, 1994, Lecture Notes in Computer Science, Springer, 1994 
  R. W. Hartenstein, et al.: A Dynamically Reconfigurable Wavefront Array Architecture for Evaluation of Expressions; Proceedings of the Int. Conference on Application-Specific Array Processors, ASAP'94, San Francisco, IEEE Computer Society Press, Los Alamitos, CA, Aug. 1994 
  A. Ast, R. W. Hartenstein, H. Reinig, K. Schmidt, M. Weber: A General Purpose Xputer Architecture derived from DSP and Image Processing; in M.A. Bayoumi (ed.): VLSI Design Methodologies for Digital Signal Processing Architectures, Kluwer Academic Publishers, p. 365-394, 1994 
  A. Ast, R. Hartenstein, et al.: Novel High Performance Machine Paradigms and Fast-Turnaround ASIC Design Methods: a Consequence of, and a Challenge to, Field-programmable Logic; Proceedings of the 2nd Int. Workshop on Field-Programmable Logic and Applications, 31.08.-02.09.92, Vienna Austria: Lecture Notes on Computer Science: "FPGAs, Architectures and Tools for Rapid Prototyping", Springer-Press, 1992 
  R. Hartenstein,A. Hirschbiel,K. Schmidt,M. Weber: A Novel Paradigm of Parallel Computation and its Use to Implement Simple High-Performance-HW; Future Generation Computer Systems 7 91/92, p. 181-198, North Holland 
  R. W. Hartenstein, M. Riedmuller, K. Schmitt, M. Weber: A Novel Asic Design Approach Based on a New Machine Paradigm; Special Issue of IEEE Journal of Solid State Circuits on ESSCIRC´90, July 1991 
  Reiner Hartenstein: Xputer: ein neues Maschinen-Paradigma für Höchstleistungsrechner; Lessacher Informatik-Kolloquien, Lessach, Österreich, 18.-21. September 1990, Springer-Press, 1991 (english: Xputer: a new Machine-Paradigm for High Performance Architectures) 
  R.W. Hartenstein, A.G. Hirschbiel, M.Weber: Xputers: Very High Throughput by Innovative Computing Principles; 5th Jerusalem Conference on Information Technology (JCIT), Jerusalem, Israel, Oktober 1990, Publ by IEEE Computer Society, Los Alamitos, CA, USA, 1990, p 43-50, 1990 
  R.W. Hartenstein, A.G. Hirschbiel, M.Weber: Rekonfigurierbare ALU erlaubt Parallelisierung auf unterster Ebene; VMEbus, 1990 (english: Reconfigurierable ALU allows Parallelizing on lowest level) 
  R.W. Hartenstein: Der Rechner aus dem Elfenbeinturm; Markt & Technik, Nr. 44/89, 1989 (english: The Machine out of the Ivory-Tower) 
  R.W. Hartenstein: Xputer: Rechner nach neuartigen Prinzipien; GI Informatik Spektrum, Springer-Press, 1989 (english: A Machine with new principles) 
  R.W. Hartenstein, A.G. Hirschbiel, M.Weber: Mapping Systolic Arrays onto the Map-Oriented Machine (MoM); in: McCanny, McWhirter, Swartzlander: Systolic Array Processors, Prentice Hall, London, 1989 
  R.W. Hartenstein, A.G. Hirschbiel, M.Weber: MoM - a partly custom-design architecture compared to standard hardware; Compeuro 89, IEEE Press, Publ by IEEE, IEEE Service Center, Piscataway, NJ, USA, 1989, p 5/7-9, 1989 
  R. Hartenstein, A. Hirschbiel, M. Weber: MOM - Map Oriented Machine; in: E. Chiricozzi & A. D'Amico: Parallel Processing and Applications, North-Holland, 1988 
  R.W. Hartenstein, A.G. Hirschbiel, M.Weber: MoM - Map Oriented Machine; Parallel Processing and Applications, North-Holland, 1988 
  R.W. Hartenstein, A.G. Hirschbiel, M.Weber: MoM - Map Oriented Machine; Hardware Accelerators for Electrical CAD, Adam Hilger, 1988 
  R.W. Hartenstein, A.G. Hirschbiel, M. Weber: A Flexible Architecture for Image Processing; Microprocessing and Microprogramming,vol 21, pp 65-72, North-Holland, 1987 
  R. Hartenstein: Das E.I.S.-Verbundprojekt: Aufbruch in die Neue Mikroelektronik; Computer-Magazin, 1984 (english: The E.I.S.-Compound-Project: Start in the New Microelectronic) 
  R. Hartenstein, R. Zaks: Microarchitecture of Computer Systems; North Holland, 1975 

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