Coarse Grain Reconfigurable Architectures

(embedded tutorial) (invited)

(paper 110)   14.02.01

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Table of Contents

Coarse Grain Reconfigurable Architectures
A Decade of Research in RC
Overview
RAs are heading for Mainstream (1)
RAs are heading for Mainstream (2)
Introduction
The History of Paradigm Shifts (1)
The History of Paradigm Shifts (2)
The History of Paradigm Shifts (3)
Coarse Grain Architectures
Why Coarse Grain instead of FPGA ?
It’s a Paradigm Shift !
Brief Overview on Architectures
Crossbar-based Architectures
M.I.T.
MATRIX Interconnect Fabrics
CHESS Array w. embedded RAM (hp)
More Research Projects
Commercial RAs
KressArray (1995)
(part of) Mapping of SNN filter
Super Pipe Networks
Future Coarse Grain RA Development 
Dynamically Reconfigurable Architectures
Dimensions of Reconfigurability
Configuration Architectures
PipeRench Architecture (CMU 1998)
Colt Architecture (P. Athanas 1996)
RA Architecture Generators
Universal RAs: is it feasible?
Communication Resource Requirements
KressArray Family Example
Generically defined Fabrics: KressArray Family
Memory Bandwidth Problems
The Memory Communication Gap
RAs: Cache does not help
Synthesizable Memory Communication
Example by Design Space Xplorer 
Programming Coarse Grain RAs
FPGA-Style Mapping for coarse grain reconfigurable arrays (1)
FPGA-Style Mapping for coarse grain reconfigurable arrays (2)
KressArray DPSS (1)
KressArray DPSS (2)
Co-Compilation
History of Loop Transformations
Loop Transformation Examples
Jürgen Becker’s Co-DE-X Co-Compiler
Fundamental Issues
Changing Models of Computing
Computer: the wrong Machine Paradigm
Soft Machine Paradigm
Machine Paradigms
Programming Language Paradigms
Conclusions
How’s next Wave ? (1)
How’s next Wave ? (2)
Co-Compilation opens new Horizon
A Decade of Research in Reconfigurable Computing
END
Title :
Coarse Grain Reconfigurable Architectures

(embedded tutorial, invited)

Authors: 
Reiner Hartenstein (speaker),
Michael Herz**,
Thomas Hoffmann,
Ulrich Nageldinger*

*) now with Infineon Technologies
**) now with Agilent

Speaker's Email: 
reiner@hartenstein.de

Speaker's Home Page:
http://xputer.de

Speaker's personal Page:
http://www.fpl.uni-kl.de/staff/hartenstein.html

Prepared for the Conference: 
Asian and South Pacific Design Automation Conference 
(ASP-DAC 2001), 
Yokohama, Japan,
January 20 - February 2, 2001

Home Page of the Conference:
http://www.aspdac.com
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

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