University of Kaiserslautern
CS department (Informatik)
Ph. D. Dissertation - 2000

Michael Herz

 
High Performance Memory 
Communication Architectures 
for Coarse-grained 
Reconfigurable Computing Systems
Abstract  V
Table of Contents  VII
1. Introduction  1
2. Coarse-grained Configurable Architectures  5
3. Memory Technologies  25
4. Earlier Address Generators  37
5. Reconfigurable Systems using Data Sequencing  73
6. A Novel Data Sequencing Concept  89
7. Data Sequencer use for Higher Memory Bandwidth  145
8. An Application Example  183
9. Conclusions  219

Appendix
A. A Development Framework for Data Sequencers  225
B. The MoPL-3 Grammar  241
C. Multibank DRAM Technology  253
D. The Map-oriented Machine with Parallel Data Access  261
List of Figures  299
List of Tables  311
List of Definitions  313
List of Symbols and Acronyms  315
References  325
Index  347