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Paper_116 
 
 for more recent papers see here   -   for all papers see here
Paper_115 
Paper 114 

R. Hartenstein (invited paper): Reconfigurable Computing - Architectures and Methodologies for System-on-Chip; SoC technology seminar "Enabling Technologies for System-on-Chip Development";  Tampere, Finland,  November 19-20, 2001
Paper 113 

R. Hartenstein (invited paper): Reconfigurable Computing: the Roadmap to a New Business Model - and its Impact on SoC Design; SBCCI 2001 - 15th Symposium on Integrated Circuits  and Systems Design, Brasilia, DF, Brazil, September 10-15, 2001 
Paper 112 

R. Hartenstein (invited keynote): Reconfigurable Computing: a New Business Model - and its Impact on SoC Design; DSD'2001 - EUROMICRO Symposium on Digital Systems Design, Warzaw, Poland, Sept. 4 - 6, 2001
Paper 111 

R. Hartenstein (embedded tutorial): A Decade of Reconfigurable Computing: a Visionary Retrospective; DATE 2001, Int'l Conference on Design Automation and Testing in Europe - and Exhibit, Munich, Germany - March 12-15, 2001
Paper 110 

R. Hartenstein (invited embedded tutorial): Coarse Grain Reconfigurable Architectures; 6th Asia and South Pacific Design Automation Conference 2001 (ASP-DAC 2001), January 30 - February 2, 2001, Pacifico Yokohama, Yokohama, Japan,
Paper 109

R. Hartenstein, Th. Hoffmann, U. Nageldinger: Design-Space Exploration of Low Power Coarse Grained Reconfigurable Datapath Array Architectures; PATMOS 2000
International Workshop - Power and Timing Modeling, Optimization and Simulation, Göttingen, Germany - September 13-15, 2000

Paper 108

R. Hartenstein, M. Herz, Th. Hoffmann, U. Nageldinger: Generation of Design Suggestions for Coarse-Grain Reconfigurable Architectures; 10th International Workshop on Field Programmable Logic and Applications, FPL '2000, Villach, Austria, Aug.27-30, 2000.

Paper 107

R. Hartenstein, M. Herz, Th. Hoffmann, U. Nageldinger: KressArray Xplorer: A New CAD Environment to Optimize Reconfigurable Datapath Array Architectures; 5th Asia and South Pacific Design Automation Conference 2000, ASP-DAC 2000, Pacifico Yokohama, Yokohama, Japan, January 25-28, 2000

Paper 106b

R. Hartenstein (eingeladener Beitrag): Der Mikroprozessor im naechsten Jahrtausend; Elektronik 49, 1, Jan. 11, 2000

Paper 106

Reiner W. Hartenstein, M. Herz, T. Hoffmann, U. Nageldinger: Mapping Applications onto reconfigurable KressArrays; 9th International Workshop on Field Programmable Logic and Applications, FPL '99, Glasgow, UK, Aug.30-Sept.2, 1999

Paper 102

 Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger: Using the KressArray for Configurable Computing; Proceedings of SPIE Vol. 3526, Conference on Configurable Computing: Technology and Applications, Boston, USA, November 2-3, 1998

Paper 99

 

 Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger: On Reconfigurable Co-Processing Units; Proceedings of Reconfigurable Architectures Workshop (RAW98), held in conjunction with 12th International Parallel Processing Symposium (IPPS-98) and 9th Symposium on Parallel and Distributed Processing (SPDP-98), Orlando, Florida, USA, March 30,1998 - Proceedings: Jose Rolim (Ed.): Parallel and Distributed Processing, Lecture Notes in Computer Science 1388, Springer-Verlag, Germany, 1998

Paper 98

 W. H. Mangione-Smith, B. Hutchings, D. Andrews, A. DeHon, C. Ebeling, R. W. Hartenstein, O. Mencer, J. Morris, K. Palem, V. Prasanna, H. Spaanenburg: Current Issues in Configurable Computing Research; IEEE Computer, Vol. 30, No. 12, December 1997

Paper 97

 Reiner W. Hartenstein (invited paper): The Microprocessor is no more General Purpose: why Future Reconfigurable Platforms will win; Proceedings of the International Conference on Innovative Systems in Silicon, ISIS'97, Austin TX, USA, Oct 8-10, 1997
Honorable Mention by E-mail

Paper 94

 Reiner W. Hartenstein, Juergen Becker, Michael Herz, Ulrich Nageldinger: Data Scheduling in Hardware/Software Co-Design for Field-programmable Accelerators; Proceedings of 7th International Workshop on Field Programmable Logic, FPL'97, London, UK, September 1-3, 1997

Paper 92

 R. Hartenstein, J. Becker, M. Herz, U. Nageldinger: An Embedded Accelerator for Real World Computing; in Proceedings of IFIP International Conference on Very Large Scale Integration, VLSI'97, Gramado, Brazil, August 26-29, 1997

Paper 90a

 R. Hartenstein: How to Survive a Possible New Design Crisis; Opening Keynote, IFIP WG10.1 & 10.7 Workshop, University of Sterling, UK, July 2-4, 1997

Paper 90

 Reiner W. Hartenstein, Jürgen Becker, Karin Schmidt: Performance Evaluation in Xputers-based Accelerators; Proc. of 4th Reconfigurable Architectures Workshop RAW-97, in conjunction with 11th Int'l. Parallel Processing Symposium (IPPS' 97), Geneva, Switzerland, April 1-5, 1997

Paper 89

 Reiner W. Hartenstein, Jürgen Becker: Performance Analysis in CoDe-X Partitioning for Structural Programmable Accelerators; Proc. of 5th Int'l Workshop on Hardware/Software Co-Design CODES/CASHE '97, Braunschweig, Germany, March 24-26, 1997

Paper 87

 Reiner W. Hartenstein, Jürgen Becker: Hardware/Software Co-Design for data-driven Xputer-based Accelerators; Proc. of 10th Int. Conf. on VLSI Design (Theme: VLSI in Multimedia Applications), January 4-7, 1997, Hyderabad, India

Paper 85

 Reiner W. Hartenstein, Jürgen Becker, Michael Herz, et al.: Co-Design and High Performance Computing: Scenes and Crisis; Proceedings of Reconfigurable Technologie for Rapid Product Development & Computing, Part of SPIE's International Symposium '96, Boston, USA, Nov. 1996
Paper 83

 Reiner W. Hartenstein, Jürgen Becker, Michael Herz, et al.: A Synthesis System for Bus-based Wavefront Array Architectures; Proceedings of ASAP 96 Application Specific Array Processors, Chicago, USA, August 1996

Paper 82

 Reiner W. Hartenstein: High-Performance Computing: Über Szenen und Krisen; GI/ITG Workshop on Custom Computing, Schloß Dagstuhl, Germany, June 1996

Paper 79

 Reiner W. Hartenstein, Jürgen Becker, et al.: An Embedded Accelerator for Real Time Image Processing; 8th EUROMICRO Workshop on Real Time Systems, L'Aquila, Italy, June 1996

Paper 77

 Reiner W. Hartenstein, Jürgen Becker, Michael Herz, et al.: A Partitioning Programming Environment for a Novel Parallel Architecture; 10th International Parallel Processing Symposium (IPPS), Honolulu, Hawaii, April 1996

Paper 75

 Reiner W. Hartenstein, Jürgen Becker, et al.: Two-Level Partitioning of Image Processing Algorithms for the Parallel Map-oriented Machine; 4th Int. Workshop on Hardware/Software Co-Design CODES/CASHE '96, Pittsburgh, USA, March 1996

Paper 74

 Reiner W. Hartenstein, Jürgen Becker, et al.: A Novel Machine Paradigm to Accelerate Scientific Computing; Special issue on Scientific Computing of Computer Science and Informatics Journal, Computer Society of India, 1996

Paper 70

 Reiner W. Hartenstein, Jürgen Becker, et al.: A Novel Hardware/Software Co-Design Framework; Journal of the Brazilian Computer Society: Special Issue on Electronic Design Automation, no.2, vol. 2, pp. 16-26, November 1995

Paper 69

 Reiner W. Hartenstein, Jürgen Becker, et al.: A Two-Level Hardware/Software Co-Design Framework for Automatic Accelerator Generation; Workshop on Design Methodologies for Microelectronics, Smolenice Castle, Slovakia, September 1995

Paper 68

 Reiner W. Hartenstein, Helmut Reinig: Novel Sequencer Hardware for High-Speed Signal Processing; Workshop on Design Methodologies for Microelectronics, Smolenice Castle, Slovakia, September 1995

Paper 67

 R. W. Hartenstein, et al.: A Scalable, Parallel, and Reconfigurable Datapath Architecture; Sixth International Symposium on IC Technology, Systems & Applications, ISIC'95, Singapore, Sept. 6-8, 1995

Paper 66

 R. W. Hartenstein, et al.: A Datapath Synthesis System for the Reconfigurable Datapath Architecture; Asia and South Pacific Design Automation Conference, ASP-DAC'95, Nippon Convention Center, Makuhari, Chiba, Japan, Aug. 29 - Sept. 1, 1995

Paper 65

 Reiner W. Hartenstein, Jürgen Becker, et al.: A Parallelizing Compilation Method for the Map-oriented Machine; Proceedings of Int. Conf. on Application Specific Array Processors, Strasbourg, France, July 1995

Paper 64

 Jürgen Becker, Reiner W. Hartenstein, et al.: High-Performance Computing Using a Reconfigurable Accelerator; Proceedings of Workshop on High Performance Computing, Montreal, Canada, July 1995 Invited reprint in Paper 80

Paper 63

 Reiner W. Hartenstein, et al.: A Reconfigurable Accelerator for 32-Bit Arithmetic; International Parallel Processing Symposium, Santa Barbara, USA, April 1995

Paper 62

 Reiner W. Hartenstein, Jürgen Becker, et al.: A Reconfigurable Machine for Applications in Image and Video Compression; Conference on Compression Technologies and Standards for Image and Video Compression, Amsterdam, The Netherlands, March 1995

Paper 61

 Reiner W. Hartenstein, Karin Schmidt: Combining Structural and Procedural Programming by Parallelizing Compilation; Proceedings of the Symposium on Applied Computing, Nashville, TN, Feb. 1995

Paper 60

 R.W. Hartenstein, et al.: A Reconfigurable Arithmetic Datapath Architecture; GI/ITG-Workshop, Schloß Dagstuhl, Bericht 303, pp. 53-59, Juli 1994

Paper 59

 R. W. Hartenstein, K. Schmidt: A Restructuring Compilation Method for the Xputer Paradigm; IWPP 94, Proceedings of the Int. Workshop on Parallel Processing, Bangalore, India, Dec. 1994

Paper 58

 Reiner W. Hartenstein, Karin Schmidt: Parallelizing Compilation for a Novel Data-Parallel Architecture; J. P. Gray, F. Naghdy (Eds.), PCAT-94, Parallel Computing: Technology and Practice, Wollongong, Australia, pp. 126-137, Nov. 1994

Paper 57

 A. Ast, J. Becker, R. W. Hartenstein, et al.: Data-procedural Languages for FPL-based Machines; 4rd Int. Workshop On Field Programmable Logic And Applications, FPL'94, Prague, Sep 7-10, 1994, Lecture Notes in Computer Science, Springer, 1994
(FPL'94 Program Chair: Reiner Hartenstein)

Paper 56

 R. W. Hartenstein, et al.: A New FPGA Architecture for Word-oriented Datapaths; 4th Int. Workshop On Field Programmable Logic And Applications, FPL'94, Prague, September 7-10, 1994, Lecture Notes in Computer Science, Springer, 1994

Paper 55

 R. W. Hartenstein, et al.: A Dynamically Reconfigurable Wavefront Array Architecture for Evaluation of Expressions; Proceedings of the Int. Conference on Application-Specific Array Processors, ASAP'94, San Francisco, IEEE Computer Society Press, Los Alamitos, CA, Aug. 1994

Paper 54

 R. W. Hartenstein, et al.: An FPGA Architecture for Word-Oriented Datapaths; Canadian Workshop on Field-Programmable Devices, FPD'94, Kingston, Ontario, June 13-16, 1994

Paper 53

 R. W. Hartenstein: Hardware / Software Codesign; Internal Report No. 246/94, University of Kaiserslautern, 1994

Paper 52

 R.W. Hartenstein, et al.: A Reconfigurable Data-Driven ALU for Xputers; IEEE Workshop on FPGAs for Custom Computing Machines, FCCM'94, Napa, CA., April 1994

Paper 51

 A. Ast, R. W. Hartenstein, H. Reinig, K. Schmidt, M. Weber: A General Purpose Xputer Architecture derived from DSP and Image Processing; in M.A. Bayoumi (ed.): VLSI Design Methodologies for Digital Signal Processing Architectures, Kluwer Academic Publishers, p. 365-394, 1994

Paper 50

 A. Ast, J. Becker, R. Hartenstein, et al.: MoPL-3: A New High Level Xputer Programming Language; 3rd Int. Workshop On Field Programmable Logic And Applications, Oxford, 7.-10. September 1993

Paper 48

 A. Ast, J. Becker, R. Hartenstein, H. Reinig, K. Schmidt, M. Weber: XPUTER: ASIC or Standard Circuit?; Invited Paper: GME Fachtagung "Mikroelektronik" in Dresden 08.10.93, 1993

Paper 47

 R. W. Hartenstein, H. Reinig, M. Weber: Design of an Address Generator; Proceedings 3rd Eurochip Workshop on VLSI Design Training, Grenoble, September 1992

Paper 46

 H. Reinig: The GAG Adress Generator; (internal report), Univ. Kaiserslautern, 1992

Paper 45

 R. Hartenstein: Avoiding Xputer Run Time Overhead by Smart Register File; (internal report), Univ. Kaiserslautern, 1992

Paper 44

 A. Ast, R. Hartenstein, et al.: Novel High Performance Machine Paradigms and Fast-Turnaround ASIC Design Methods: a Consequence of, and a Challenge to, Field-programmable Logic; Proceedings of the 2nd Int. Workshop on Field-Programmable Logic and Applications, 31.08.-02.09.92, Vienna Austria: Lecture Notes on Computer Science: "FPGAs, Architectures and Tools for Rapid Prototyping", Springer-Press, 1992

Paper 43

 A. Ast, R. Hartenstein, H. Reinig, K. Schmidt, M. Weber: A Novel High-performance Machine Paradigm and ASIC Design Methodology; Int. Design Automation Workshop ("Russian Workshop"), 29.- 30.06.92, Moskau, 1992

Paper 42

 R. Hartenstein,A. Hirschbiel,K. Schmidt,M. Weber: A Novel Paradigm of Parallel Computation and its Use to Implement Simple High-Performance-HW; Future Generation Computer Systems 7 91/92, p. 181-198, North Holland Invited reprint of Paper 31

Paper 41

 R. W. Hartenstein, M. Riedmuller, K. Schmitt, M. Weber: A Novel Asic Design Approach Based on a New Machine Paradigm; Report no. 212/91, Univ. Kaiserslautern, 1991

Paper 40

 R. W. Hartenstein, M. Riedmuller, K. Schmitt, M. Weber: A Novel Asic Design Approach Based on a New Machine Paradigm; Special Issue of IEEE Journal of Solid State Circuits on ESSCIRC´90, July 1991

Paper 39

 R. W. Hartenstein, K. Schmidt, H. Reinig, M. Weber: A Novel Compilation Technique for a Machine Paradigm Based on Field-Programmable Logic; in Will Moore, Wayne Luk (ed.): FPGAs; Oxford 1991 International Workshop on Field Programmable Logic and Applications, Abingdon EE&CS Books, Abingdon, 1991

Paper 38

 Reiner Hartenstein: Xputer: ein neues Maschinen-Paradigma für Höchstleistungsrechner; Lessacher Informatik-Kolloquien, Lessach, Österreich, 18.-21. September 1990, Springer-Press, 1991 (english: Xputer: a new Machine-Paradigm for High Performance Architectures)

Paper 37

 R.W. Hartenstein, H. Reinig, M. Riedmuller, K. Schmidt: A Novel Computational Paradigm: Much More Efficient Than Von Neumann Principles; 13th IMACS World Congress, Dublin Ireland, 1991

Paper 36

 R.W. Hartenstein, A.G. Hirschbiel, M. Riedmueller, K. Schmidt, M.Weber: A High Performance Machine Paradigm Based on Auto-Sequencing Data Memory; HICSS-24, Hawaii Int. Conference on System Sciences, Koloa Hawaii, 1991
Second Best Paper Award (Honorable Mention)

Paper 35

 R.W. Hartenstein, A.G. Hirschbiel, M. Riedmuller, K. Schmidt, M.Weber: A Novel Paradigm of Parallel Computation and its Use to Implement Simple High Performance Hardware; Univ. Kaiserslautern, 1990

Paper 34

 R.W. Hartenstein, A.G. Hirschbiel, M. Riedmuller, K. Schmidt, M.Weber: A Flexible Hardware Accelerator and its Applications in EDA; 16th CAVE Workshop in Gent, Belgien, 1990

Paper 33

 R.W. Hartenstein, A.G. Hirschbiel, M.Weber: Xputers: Very High Throughput by Innovative Computing Principles; 5th Jerusalem Conference on Information Technology (JCIT), Jerusalem, Israel, Oktober 1990, Publ by IEEE Computer Society, Los Alamitos, CA, USA, 1990, p 43-50, 1990

Paper 32

 R.W. Hartenstein, A.G. Hirschbiel, K.Lemmert, M. Riedmuller, K. Schmidt, M.Weber: Xputer Use in Image Processing and Digital Signal Processing; SPIE Visual Communication and Image Processing'90, Lausanne, Schweiz, Publ. by Int. Soc. for Optical Engineering, Bellingham, WA, USA, p 778 -789, 1990

Paper 31

 R.W. Hartenstein, A.G. Hirschbiel, M.Weber: A Novel Paradigm of Parallel Computation and its Use to Implement Simple High Performance Hardware; InfoJapan'90- International Conference memorating the 30th Anniversary of the Computer Society of Japan, Tokyo, Japan, 1990 Invited reprint in Paper 42

Paper 30

 R.W. Hartenstein, A.G. Hirschbiel, K. Schmidt, M. Weber: A Novel ASIC Design Approach based on a New Machine Paradigm; European Solid-State Circuits Conference `90, Grenoble, Frankreich

Paper 29

 

 R.W. Hartenstein, A.G. Hirschbiel, M. Riedmuller, K. Schmidt, M.Weber: Automatic Synthesis of Cheap Hardware Accelerators for Signal Processing and Image Preprocessing; 12. DAGM-Symposium Mustererkennung, Oberkochen-Aalen, 1990

Best Paper and Best Presentation Award (DM 1000.--) Speaker: Michael Weber 

Paper 28

 R.W. Hartenstein, A.G. Hirschbiel, M.Weber: A Novel Paradigm of Parallel Computation and its Use to Implement Simple High Performance Hardware; CONPAR '90 - VAPP IV, Zurich, 1990

Paper 27

 R.W. Hartenstein, A.G. Hirschbiel, M.Weber: The Machine Paradigm of Xputers and its Application to Digital Signal Processing Acceleration; 1990 Int. Conference on Parallel Processing, St. Charles, Illinois , 1990

Paper 26

 R.W. Hartenstein, A.G. Hirschbiel, M.Weber: Using Xputers as Universal Accelerators for Neuro Network Simulation and its Applications; Int. Neural Network Conference, INNC 90, Paris, 1990

Paper 25

 A. Ast, R.W. Hartenstein, A.G. Hirschbiel, M. Riedmuller, K. Schmidt, M.Weber: Using Xputers as Inexpensive Universal Accelerators in Digital Signal Processing; Bilkent'90 Int. Conference on New Trends in Communication, Control and Signal Processing, Ankara, Turkey, 1990

Paper 24

 R.W. Hartenstein, A.G. Hirschbiel, M.Weber: The Machine Paradigm of Xputers and its Application to Digital Signal Processing Acceleration; Int. Workshop on Algorithms and Parallel VLSI Architectures, Pont-ý-Mousson, France, 1990

Paper 23

 R.W. Hartenstein, A.G. Hirschbiel, M.Weber: Xputers - An Open Family of Non von Neumann Architectures; Proc. of 11th ITG/GI-Conference: Architektur von Rechensystemen, VDE-Verlag, 1990

Paper 22

 R.W. Hartenstein, A.G. Hirschbiel, M.Weber: Rekonfigurierbare ALU erlaubt Parallelisierung auf unterster Ebene; VMEbus, 1990 (english: Reconfigurierable ALU allows Parallelizing on lowest level)

Paper 21

 R.W. Hartenstein: Der Rechner aus dem Elfenbeinturm; Markt & Technik, Nr. 44/89, 1989 (english: The Machine out of the Ivory-Tower)

Paper 20

 R.W. Hartenstein: Xputer: Rechner nach neuartigen Prinzipien; GI Informatik Spektrum, Springer-Press, 1989 (english: A Machine with new principles)

Paper 19

 R.W. Hartenstein, A.G. Hirschbiel, M.Weber: Mapping Systolic Arrays onto the Map-Oriented Machine (MoM); in: McCanny, McWhirter, Swartzlander: Systolic Array Processors, Prentice Hall, London, 1989

Paper 18

 R.W. Hartenstein, A.G. Hirschbiel, M.Weber: A Pseudo Parallel Architecture for Systolic Algorithms; Proc. of the IFIP Workshop on Parallel Architectures on Silicon, Grenoble, 1989

Paper 17

 R.W. Hartenstein, A.G. Hirschbiel, M.Weber: A Pseudo Parallel Architecture for Systolic Algorithms; Proc. of the Int. Conference on VLSI and CAD, Seoul (Korea), 1989

Paper 16

 R.W. Hartenstein, A.G. Hirschbiel, M.Weber: Xputers - An Open Family of Non von Neumann Architectures; Report no. 195/89, Univ. Kaiserslautern, 1989

Paper 15

 R.W. Hartenstein, A.G. Hirschbiel, M.Weber: MoM - a partly custom-design architecture compared to standard hardware; Compeuro 89, IEEE Press, Publ by IEEE, IEEE Service Center, Piscataway, NJ, USA, 1989, p 5/7-9, 1989

Paper 14

 R. Hartenstein, A. Hirschbiel, M. Weber: MOM - Map Oriented Machine; in: E. Chiricozzi & A. D'Amico: Parallel Processing and Applications, North-Holland, 1988

Paper 13

 R.W. Hartenstein, A.G. Hirschbiel, M.Weber: MoM - Map Oriented Machine; Parallel Processing and Applications, North-Holland, 1988

Paper 12

 R.W. Hartenstein, A.G. Hirschbiel, M.Weber: MoM - Map Oriented Machine, An Innovative Computing Architecture; Report Nr. 181/88, Univ. Kaiserslautern, 1988

Paper 11

 R.W. Hartenstein, A.G. Hirschbiel, M.Weber: MoM - Map Oriented Machine; Hardware Accelerators for Electrical CAD, Adam Hilger, 1988

Paper 10

 R. Hartenstein, A. Hirschbiel, M. Weber: A Flexible Architecture for Image Processing; Proceedings of the EUROMICRO Symposium, Portsmouth, 1987

Paper 09

 R. Hartenstein, A. Hirschbiel, M. Weber: MOM - Map Oriented Machine; Conference on Parallel Processing and Applications, L'Aquila, Italien, 1987

Paper 08

 R. Hartenstein, A. Hirschbiel, M. Weber: MOM - Map Oriented Machine; Proceedings of the International Workshop on Hardware Accelerators, 1987

Paper 07

 R.W. Hartenstein, A.G. Hirschbiel, M. Weber: A Flexible Architecture for Image Processing; Microprocessing and Microprogramming,vol 21, pp 65-72, North-Holland, 1987

Paper 06a

 Bastian, K. P.; Hartenstein, R. W.; Nebel, W.: Innovative Schaltungstechnik statt Software - Shuffle Sort: VLSI-Beispiel eines Sortierers; VDI/VDE-Gesellschaft für Meß- und Regelungstechnik (GMR), Tagung 'Mikroelektronik in der Automatisie-rungstechnik', Baden-Baden; VDI-Ber. Nr. 550, Düsseldorf, 1985

Paper 06

 J. Bl–del, R. Hauck, R. W. Hartenstein, M. Ryba, H. Salzmann, M. Weber: PISA: Pixel-oriented System for Layout Analysis Benutzeranleitung; Department of Computer Science & Engineering, Univ. Kaiserslautern, 1985 (english: PISA: Pixel-oriented System for Layout Analysis User-Guidance)

Paper 05

 R. Hartenstein: Das E.I.S.-Verbundprojekt: Aufbruch in die Neue Mikroelektronik; Computer-Magazin, 1984 (english: The E.I.S.-Compound-Project: Start in the New Microelectronic)

Paper 04

 R. Hartenstein, R. Hauck, A. Hirschbiel, W. Nebel, M. Weber: PISA, a CAD package and special hardware for pixel-oriented layout analysis; Proceedings ICCAD - Int. Conference on CAD, Sta. Clara, California, 1984

Paper 03

 R. Hartenstein, R. Hauck, A. Hirschbiel, W. Nebel, M. Weber: PISA, a CAD package and special hardware for pixel-oriented layout analysis; Report, Univ. Kaiserslautern, 1984

Paper 02

 P. Braun, R. Hartenstein, J. Hassdenteufel: Pixel-oriented Layout Analysis: Semi-Automatic Analyzer Generation for Design Rule Check and Circuit Extraction; Univ. Kaiserslautern, 1983

Paper 01

 P. Braun, E. Ewald, J. Hassdenteufel, R. Hauck, A. Hirschbiel, M. Weber: DRC-KL-Programmsystem; Univ. Kaiserslautern, 1983 (english: DRC-KL-Program-System)

Paper 00
 R. Hartenstein, R. Zaks: Microarchitecture of Computer Systems; North Holland, 1975
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