8th Reconfigurable Architectures Workshop (RAW 2001)

San Francisco Airport Hyatt, April 27, 2001

Advance Program


8.30

Welcome and Introduction

Invited Talk
Attacking the Semantic Gap Between Application Programming Languages and Configurable Hardware G. Snider,Hewlett-Packard Laboratories, Palo Alto

Session 1: Algorithms and Applications

9.30 Fast ant colony optimization on reconfigurable processor arrays
D. Merkle, M. Middendorf, University of Karlsruhe
10.00

Coffee break

10.30 Scalable space/time-shared stream-processing on the run-time reconfigurable PCA architecture,
N. Imlig, T. Shiozawa, K. Nagami, Y. Nakane, R. Konishi, H. Ito, A. Nagoya, NTT Network Innovation Laboratories
11.00 A run-time reconfigurable array of multipliers architecture,
R. Lin, SUNY-Geneseo
11.30 Implementation of very large dataflow graphs on a reconfigurable architecture for robotic applications
J.P. David, T. Postiau, P. Fisette, J.D. Legat, Université Catholique de Louvain

Session 2: Architectures and run-time systems

12.00 Global memory mapping for FPGA-based reconfigurable systems
I. Ouaiss, R. Vemuri, University of Cincinnati
12.30

Lunch break

13.30 Minimizing routing configuration cost in dynamically reconfigurable FPGAs
D. Rakhmatov, S.B.K. Vrudhula, University of Arizona
14.00 Strategically programmable systems
S. Memik, M. Sarrafzadeh, Northwestern University & UCLA
14.30 Discussion: Reconfigurable architectures in overall system architecture
15.00

Coffee break

Session 3: Design and programming

16.00 Loop fusion and temporal common subexpression elimination in window-based loops
J. Hammes, A.P.W. Bohm, C. Ross, M. Chawathe, B. Draper, R. Rinker, W. Najjar, Colorado State University
16.30 Cores and anti-cores: Using Jbits as part of a mainstream design flow
P.B. James-Roxby, D.J. Downs, Xilinx, Inc.
17.00 Java debug hardware models using Jbits
J. Ballagh, P. Athanas, E. Keller, Virginia Tech & Xilinx, Inc.
17.30 Discussion: Debugging and testing of reconfigurable systems