Advance Program

4th Reconfigurable Architectures Workshop (RAW'97)

April 1, 1997, Geneva, Switzerland

to be held in conjunction with 11th International Parallel Processing Symposium
(IPPS-97)

(Sponsored by IEEE Technical Committee on Parallel Processing)

Program Chair: Reiner W. Hartenstein, Kaiserslautern University
Workshop Chair: Viktor K. Prasanna, University of Southern California

Text version

This workshop is the 4th one in a series held at Cancun, Mexico (1994), Santa Barbara, California (1995), and Honolulu, Hawaii (1996). RAW-97 is part of the 11th International Parallel Processing Symposium (IPPS-97), held April 1 - 5, 1997 at University of Geneva, Switzerland. RAW-97 will be held at April 1, the first day of IPPS-97. RAW-97 is one of 14 specialized workshops held first or last day of IPPS-97.

Goals and Visions of the Workshop

The recent decade has witnessed enormous technological advances, a deeper appreciation of the power of the use of reconfigurable technology platforms, and a better understanding of computing in time and in space. The building of reconfigurable systems can only be achieved by building on the experience in different areas, and close interaction between them to identify and solve the remaining problems.

The primary objective of this workshop is to provide opportunity for creative interaction between researchers actively involved in the fabrication, design, applications and enabling technologies of reconfigurable architectures.

Program Committee

Advance Program

The workshop features several sessions of submitted paper presentations as well as invited papers.

Session 1
8.40 Invited talk: V. K. Prasanna*, K. Bondalapati, University of Southern California (USA): Reconfigurable Meshes: Theory and Practice
9.00 G. Brebner*, University of Edinburgh (UK) CHASTE: a Hardware / Software Co-design Testbed for the Xilinx XC6200
9.20 K. J. Page, J. F. Arrigo, P. M. Chau*, University of California at San Diego (USA) Index Mapping for Reconfigurable Communications Architectures
9.40 M. A. Perkowski, L. Jozwiak*, D. Foote, Portland State University (USA) FPGA Architecture for Constructive Induction approach to Machine Learning and other Discrete Optimization problems
10.00 T. Ramesh*, Saginaw Valley State University (USA) FPGA Synthesis for a Clustered Reconfigurable System
10.10 D. Mange, M. Goeke, D. Madon, A. Stauffer*, G. Tempesti, Swiss Federal Inst. of Technology (CH) FPPA: A Field-Programmable Processor Array with Self-Repair and Self-Reproducing Properties
10.20 End of Session 1
Session 2
10.40 Invited talk: T. Kean*, J. Gray, Xilinx Development Corp. (UK) The Case for Reconfigurable Logic Based Servers no
paper
11.00 G. Milne*, D. George, B. Gunther, University of South Australia (AUS) Experiments in Traffic Simulation using Reconfigurable Computing
11.20 R. W. Hartenstein, J. Becker*, K. Schmidt, University of Kaiserslautern (D) Performance-Evaluation in Xputer-based Accelerators
11.40 A. A. Duncan*, D. C. Hendry, P. Gray, University of Aberdeen (UK) Architectural Issues for High Level Synthesis of DSP Algorithms onto Multiple FPGAs
11.50 C. Hochberger, R. Hoffmann*, K.-P. Voelkmann, J. Steuerwald, Technical University of Darmstadt (D) The CEPRA-1X Cellular Processor
12.00 End of Session 2
Session 3
13.20 Invited talk: W. Mangione-Smith*, B. Hutchins*, University of California at LA (USA) Reconfigurable Architectures: The Road Ahead
13.40 R. Lin*, S. Olariu, State University of New York at Geneseo (USA) Efficient Hardware/Software Partitioning of Leighton's Column Sort
14.00 M. Weinhardt*, University of Karlsruhe (D) Compilation and Pipeline Synthesis for Reconfigurable Architectures
14.20 T. Horita*, I. Takanami, Iwate University (JP) Neuron's Faults in Neural Approach for Reconfiguring 1 1/2-Track Mesh Arrays
14.30 L. E. LaForge*, Embry Riddle Aeronautical University (USA) Configuration for Fault Tolerance
14.40 End of Session 3
Session 4
15.00 Invited talk: R. Kress*, Siemens Research (D): Configurable Computing: The Software Gap
15.20 Invited talk: J. W. Rozenblit, T. Ewing*, University of Arizona at Tucson (USA) Simulation-Based Verification in HW/SW Codesign: An FPGA Approach
15.40 U. Eckhardt, R. Merker, Technical University of Dresden (D) Co-Partitioning - A Method for Hardware / Software Codesign for Scalable Systolic Arrays
16.00 I. Takanami*, T. Horita, Iwate University (JP) A Reconfigurable Architecture - Reconfiguration of Mesh-Arrays with PE and Link Faults
16.20 M. Chatter*, neoRam LLC (USA) Self-Modifying, On-the-Fly-Reconfigurable Logic
16.30 A. Tyagi*, Iowa State University (USA) Reconfigurable Memory Queues / Computing Units Architecture
16.40 End of Session 4 and workshop

Registration:

RAW-97 is part of the 11th International Parallel Processing Symposium IPPS-97. Registration for IPPS-97 includes attendance to RAW-97. To register electronically, please visit the IPPS homepage.

For Further Information,

please contact any of the workshop co-chairs:


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