Workshop Co-chairs: Reiner W. Hartenstein, Viktor K. Prasanna
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This workshop is the 4th one in a series held at Cancun, Mexico (1994), Santa Barbara, California (1995), and Honolulu, Hawaii (1996). RAW-97 is part of the 11th International Parallel Processing Symposium (IPPS-97), held April 1 - 5, 1997 at University of Geneva, Switzerland. RAW-97 will be held at April 1, the first day of IPPS-97. RAW-97 is one of 14 specialized workshops held first or last day of IPPS-97.
The recent decade has witnessed enormous technological advances, a deeper appreciation of the power of the use of reconfigurable technology platforms, and a better understanding of computing in time and in space. The building of reconfigurable systems can only be achieved by building on the experience in different areas, and close interaction between them to identify and solve the remaining problems.
The primary objective of this workshop is to provide opportunity for creative interaction between researchers actively involved in the fabrication, design, applications and enabling technologies of reconfigurable architectures.
The workshop will feature several sessions of submitted paper presentations and proceedings will be available at the symposium and by public ftp. Authors are invited to submit manuscripts which demonstrate original and on-going research in areas of Reconfigurable Architectures, implementations, algorithms and applications. The topics of interest include, but are not limited to:
We are witnessing the beginning of a paradigm change. Hardware has become soft. A second world of programming joins the traditional procedural programming: the world of structural programming. In the long term this will revolutionize the entire computing science. The mainly procedurally oriented traditional computing science will end up in a duality of computing in time and computing in space. The crystalization point of this overlap is already here. It is the area of systolic array synthesis, where time and space appear within the same formula, and, which provides first mappings between both worlds. (Systolic arrays stress computing in space, because the locality of an operation in a particular PE is a central concept. In classical parallel computing (except SIMD and similar) locality is not interesting, since processors have addresses.)
This is just the beginning. You are encouraged to submit your cool ideas, your hot implementations, and your exciting visions - to accelerate this march to new horizons.
Until recently the populations of the R&D scene of parallel computing or high performance computing on one side, and the scenes dealing with reconfigurable hardware platforms have been non-overlapping. But both populations have the same goal: high performance by parallelism. Until recently calls for papers and participants on reconfigurable platforms, systems, and applications attracted only hardware experts. Most of them practice hardware / software co-design: linking structurally programmed accelerator hardware to traditional software running on a procedurally programmed host system. But high performance people, supercomputing people, parallel computing people, etc. went only to their own conferences. Until recently only a few of them had heard anything about FPGAs and other reconfigurable platforms and how to use them for speed-up. The time has come to bridge that gap: we need your help.
All papers will be reviewed. Please, send five (5) copies of complete paper (uip to 10 single spaced, single sided pages) to:
Electronic submissions (in postscript format) are encouraged and should be sent to firstname.lastname@example.org and email@example.com (please, use both, simultaneously)
The workshop proceedings will be published by a professional publisher, taking care of ISBN number and Library of Congress catalog number.
please contact any of the workshop co-chairs:
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