From nageldin@herakles Fri Mar 14 19:29:36 1997 Return-Path: Received: from herakles.SUN-AGHART by odysseus.SUN-AGHART (4.1/SMI-4.1) id AA02973; Fri, 14 Mar 97 19:29:35 +0100 Received: by herakles.SUN-AGHART (4.1/SMI-4.1) id AA02577; Fri, 14 Mar 97 19:29:36 +0100 Date: Fri, 14 Mar 97 19:29:36 +0100 From: nageldin@herakles (Ulrich Nageldinger) Message-Id: <9703141829.AA02577@herakles.SUN-AGHART> To: michael@odysseus Subject: Und wieder ein neues RAW-programm X-Mozilla-Status: 0005 Content-Length: 7699 Hier ist die neueste Version des RAW-programms. Aenderungen nur bei 10.40, 15.20 und 15.40. Gruss, Ulrich ------------------------------------------------------------------------------ R e c o n f i g u r a b l e A r c h i t e c t u r e s A D V A N C E P R O G R A M 4th Reconfigurable Architectures Workshop (RAW-97) April 1, 1997, Geneva, Switzerland to be held in conjunction with 11th International Parallel Processing Symposium (IPPS-97) (Sponsored by IEEE Technical Committee on Parallel Processing) http://cuiwww.unige.ch/~ipps97/ Program Chair: Reiner W. Hartenstein, Kaiserslautern University Workshop Chair: Viktor K. Prasanna, University of Southern California This workshop is the 4th one in a series held at Cancun, Mexico (1994), Santa Barbara, California (1995), and Honolulu, Hawaii (1996). RAW-97 is part of the 11th International Parallel Processing Symposium (IPPS-97), held April 1 - 5, 1997 at University of Geneva, Switzerland. RAW-97 will be held at April 1, the first day of IPPS-97. RAW-97 is one of 14 specialized workshops held first or last day of IPPS-97. See http://xputers.informatik.uni-kl.de/RAW/RAW97.html ------------------------------------------------------------------------------ PROGRAM COMMITTEE ------------------------------------------------------------------------------ Peter Athanas, Virginia Tech (USA) Klaus Buchenrieder, Siemens Research (D) Steven Casselman, Virtual Computer Corp. (USA) Bernard Courtois, Univ. Grenoble (F) Andre' DeHon, Univ. of California, Berkeley (USA) Hossam Elgindy, Univ. of Newcastle (AUS) Rolf Ernst, Univ. Braunschweig (D) Manfred Glesner, TH Darmstadt (D) John Gray, Xilinx Corp. (UK) Reiner Hartenstein, Univ. Kaiserslautern (D) Friedel Hossfeld, Forschugszentrum Juelich GmbH (D) Brad L Hutchings, Brigham Young University (USA) Rong Lin, State Univ. of New York, Geneseo (USA) Viktor Prasanna, Univ. of Southern California (USA) Michal Servit, Techn. Univ. Prague (CR) John Villasenor, Univ. of California, Los Angeles (USA) ------------------------------------------------------------------------------ ADVANCE PROGRAM ------------------------------------------------------------------------------ The workshop features several sessions of submitted paper presentations as well as invited papers. The following schedule is subject to changes. SESSION 1: ---------- 8.40 Invited talk: V.K. PRASANNA, K. Bondalapati University of Southern California (USA) Reconfigurable Meshes: Theory and Practice 9.00 G. BREBNER, University of Edinburgh (UK) CHASTE: a Hardware / Software Co-design Testbed for the Xilinx XC6200 9.20 P.M. CHAU, K.J. Page, J.F. Arrigo University of California at San Diego (USA) Index Mapping for Reconfigurable Communications Architectures 9.40 L. JOZWIAK, M.A. Perkowski, D. Foote, Portland State University (USA) Architecture of a Programmable FPGA Coprocessor for Constructive Induction Approach to Machine Learning and other Discrete Optimization Problems 10.00 T. RAMESH, Saginaw Valley State University (USA) FPGA Synthesis for a Clustered Reconfigurable System 10.10 A. STAUFFER, D. Mange, M. Goeke, D. Madon, G. Tempesti, Swiss Federal Inst. of Technology (CH) FPPA: A Field-Programmable Processor Array with Self-Repair and Self-Reproducing Properties 10.20 End of Session 1 SESSION 2: ---------- 10.40 Invited talk: T. KEAN, J. Gray, Xilinx Development Corp. (UK) The Case for Reconfigurable Logic Based Servers 11.00 G. MILNE, D. George, B. Gunther, University of South Australia (AUS) Experiments in Traffic Simulation using Reconfigurable Computing 11.20 J. BECKER, R.W. Hartenstein, K. Schmidt, University of Kaiserslautern (D) Performance-Evaluation in Xputer-based Accelerators 11.40 A.A. DUNCAN, D.C. Hendry, P. Gray, University of Aberdeen (UK) Architectural Issues for High Level Synthesis of DSP Algorithms onto Multiple FPGAs 11.50 R. HOFFMANN, C. Hochberger, K.-P. Voelkmann, J. Steuerwald, Technical University of Darmstadt (D) The CEPRA-1X Cellular Processor 12.00 End of Session 2 SESSION 3: ---------- 13.20 Invited talk: W. MANGIONE-SMITH, B. HUTCHINGS, University of California at LA / Brigham Young University (USA) Configurable Computing: The Road Ahead 13.40 R. LIN, S. Olariu, State University of New York at Geneseo (USA) Efficient Hardware/Software Partitioning of Leighton's Column Sort 14.00 M. WEINHARDT, University of Karlsruhe (D) Compilation and Pipeline Synthesis for Reconfigurable Architectures 14.20 T. HORITA, I. Takanami, Iwate University (JP) Neuron's Faults in Neural Approach for Reconfiguring 1 1/2-Track Mesh Arrays 14.30 L.E. LAFORGE, Embry Riddle Aeronautical University (USA) Configuration for Fault Tolerance 14.40 End of Session 3 SESSION 4: ---------- 15.00 Invited talk: R. KRESS, Siemens Research (D) Configurable Computing: The Software Gap 15.20 Invited talk: T. EWING, J.W. Rozenblit University of Arizona at Tucson (USA) Simulation-Based Verification in HW/SW Codesign: An FPGA Approach 15.40 U. Eckhardt, R. Merker, Technical University of Dresden (D) Co-Partitioning - A Method for Hardware / Software Codesign for Scalable Systolic Arrays 16.00 I. TAKANAMI, T. Horita, Iwate University (JP) A Reconfigurable Architecture - Reconfiguration of Mesh-Arrays with PE and Link Faults 16.20 M. CHATTER, neoRam LLC (USA) Self-Modifying, On-the-Fly-Reconfigurable Logic 16.30 A. TYAGI, Iowa State University (USA) Reconfigurable Memory Queues / Computing Units Architecture 16.40 End of Session 4 and workshop ------------------------------------------------------------------------------ REGISTRATION ------------------------------------------------------------------------------ RAW-97 is part of the 11th International Parallel Processing Symposium IPPS-97. Registration for IPPS-97 includes attendance to RAW-97. To register electronically, please visit the IPPS homepage at www.ippsxx.org. ------------------------------------------------------------------------------ FURTHER INFORMATION ON RAW-97 ------------------------------------------------------------------------------ For Further Information, please contact any of the workshop co-chairs: Reiner W. Hartenstein Universitaet Kaiserslautern (Germany) E-mail: hartenst@rhrk.uni-kl.de and abakus@informatik.uni-kl.de (please, use both, simultaneously), FAX: +49 631 205 2640 and: +49 7251 14823 (please, use both, simultaneously) Viktor K. Prasanna University of Southern California (USA) E-mail: prasanna@ganges.usc.edu FAX: +1 213 740 4418 For updates of your information also frequently check the web html page: http://xputers.informatik.uni-kl.de/RAW/RAW97.html - for ASCII version see: http://xputers.informatik.uni-kl.de/RAW/RAW97/RAW_adv_prg.txt