5th Reconfigurable Architectures Workshop (RAW'98) 
March 30, 1998, Orlando, Florida, USA

Advance Program
 
Session 1: Application Development Methods I
9.00 G. Ghare, S.-Y. Lee; Auburn University, USA: 
Dynamic Reconfiguration of a PMMLA (Pipeline of Multiprocessor Modules based on a Linear Array) for High-Throughput Applications
9.20 W. Fornaciari, V. Piuri; Politecnico di Milano, Italy 
Virtual FPGAs: some steps behind the physical barriers
9.40 P. Baglietto, M. Maresca, M. Migliardi; DIST - University of Genoa, Italy 
A Parallel Algorithm for Minimum Cost Path Computation on Polymorphic Processor Array
10.00 End of Session 1 / Coffee break
Session 2: Application Development Methods II
10.30 J. Walrath, R. Vemuri; University of Cincinnati, USA 
A Performance Modeling and Analysis Environment for Reconfigurable Computers
10.50 G. Brebner, A. Donlin; University of Edinburgh, Scotland 
Runtime Reconfigurable Routing
11.10 I. Ouaiss, S. Govindarajan, V. Srinivasan, M. Kaul, R.Vemuri; U. Cincinnati, USA 
An Integrated Partitioning and Synthesis System for Dynamically Reconfigurable Multi-FPGA Architectures
11.30 J. Spillane, H. Owen; Georgia Institute of Technology, USA 
Temporal Partitioning for Partially-Reconfigurable-Field-Programmable Gate Arrays
11.50 D. Davis, M. Barr, T. Bennett, S. Edwards, J. Harris, I. Miller, C. Schank;  TSI Inc., USA 
A Java Development and Runtime Environment for Reconfigurable Computing
12.10  K. Rath, J. Li; University of Texas at Dallas, USA 
Synthesizing Reconfigurable Sequential Machines Using Tabular Model
12.30 End of Session 2 / Lunch break
Session 3: Reconfigurable Architectures I
14.00 A. Abnous, K. Seno, Y. Ichikawa, M. Wan, J. Rabaey; University of California,  Berkeley, USA 
Evaluation of a Low-Power Reconfigurable DSP Architecture
14.20 A. Kirschbaum, J. Becker, M. Glesner; U. of Technology, Darmstadt, Germany 
A Reconfigurable Hardware-Monitor for Communication-Analysis in Distributed Real-Time Systems
14.40 R. Hartenstein, M. Herz, T. Hoffmann, U. Nageldinger; U. Kaiserslautern, Germany: 
On Reconfigurable Co-Processing Units
15.00 End of Session 3 / Coffee break
Session 4: Reconfigurable Architectures II
15.30 S.M. Scalera, J.J. Murray, S. Lease; Sanders, Lockheed, USA 
A Mathematical Benefit Analysis of Context Switching Reconfigurable Computing
15.50 B. Pudipeddi, A.L. Abbott, P.M. Athanas; Virginia Tech, USA 
A Configurable Computing Approach Towards Real-time Target Tracking
16.10 Y. Shibata, H. Miyazaki, X.-p. Ling, H. Amano; Keio University, Japan 
HOSMII: a Virtual Hardware Integrated with DRAM
16.30 J.-L. Beuchat, J.-O. Haenni, E. Sanchez; EPFL, Switzerland 
Hardware Reconfigurable Neural Networks
16.50 C. Steckel, M. Middendorf, H. ElGindy, H. Schmeck; U. Karlsruhe, Germany 
A Simulator for the Reconfigurable Mesh Architecture
17.10 R. Kolla, O. Springauf; University Wuerzburg, Germany 
PACE: Processor Architectures for Circuit Emulation
17.30 End of Session 4 and workshop