R. Hartenstein (invited book): Fundamentals of
Structured Hardware Design - A Design Language Approach at Register Transfer
Level; Amsterdam / New York, North Holland / American Elsevier, 1977
R. Hartenstein (invited book): Hardware Description
Languages; (Volume no. 7 of the book series "Advances in CAD for VLSI")
Amsterdam / New York, North Holland / American Elsevier, 1986
--- half authored / half edited
Books, edited:
R. Hartenstein, H. Gruenbacher: Field-Programmable
Logic and Applications - The Roadmap to Reconfigurable Computing;
Heidelberg / New York, Springer Verlag, 2000
P. Lysaght, J. Irvine, R. Hartenstein: Field-Programmable
Logic and Applications, Heidelberg / New York, Springer-Verlag, 1999
R. Hartenstein, A Keevallik: Field-Programmable Logic
and Applications: From FPGAs to Computing Paradigm; Heidelberg / New York,
Springer-Verlag, 1998
R. Hartenstein, M. Glesner: Field-Programmable Logic;
Heidelberg / New York, Springer-Verlag, 1996
R. Hartenstein, M. Servít: Field-Programmable
Logic: Architectures, Synthesis, and Applications; Heidelberg / New York,
Springer-Verlag, 1998
H. Gruenbacher, R. Hartenstein: Field-Programmable
Gate Arrays: Architectures and Tools for Rapid Prototyping; Heidelberg
/ New York, Springer-Verlag, 1993.
R. Hartenstein,. D. Auvergne: Power and Timing Modelling
for Performance of Integrated Circuits, Bruchsal / Chicago, ITpress,
1993
R. Hartenstein, M. Breuer: Computer Hardware Description
Languages and their Applications; Amsterdam / New York, North Holland /
American Elsevier, 1981
R. Hartenstein, R. Zaks: Microarchitecture of
Computer Systems ; Amsterdam / New York, North Holland / American
Elsevier, 1975
Books authored in German
language:
R. Hartenstein*: No Fancy on High Tech; Bruchsal /
Chicago, ITpress, 1996 (in German: Null Bock auf High Tech )
R. Hartenstein (bestselling academic course
text book)*: VLSI Computer System Design; Bruchsal / Chicago, ITpress,
1993 (in German language: Wozu noch Mikro-Chips? Einfuehrung in Methoden
der Technischen Informatik)
Keynotes
(documented)
Are we ready for the Breakthrough ?; 10th
Reconfigurable Architectures Workshop 2003 (RAW 2003), Nice, France, April
22, 2003
Data-Stream-based Computing and Morphware;
Joint 33rd Speedup and 19th PARS Workshop (Speedup / PARS 2003), Basel,
Switzerland, March 19 - 21, 2003
Disruptive Trends by Custom Compute Engines.
The 12th International Conference on Field Programmable Logic and Application
FPL 2002, September 2 - 4, 2002, La Grande-Motte (Montpellier,
France)
Reconfigurable Computing: urging
a revision of basic CS curricula; Workshop on Logic and Synthesis
for Programmable Devices - WLSPD2002, Las Vegas, USA, 6-8 August,
2002
(in German language) Stream-based Computing: Antimaterie
der Informatik (Stream-based Computing: Antimatter of Informatics); 60th
semester anniversary workshop of the chair "Informatik I" (Prof. Reusch),
University of Dortmund, July 18. - 19, 2002
Stream-based Computing - Antimatter of Informatics;
First International Conf. on Intelligent Computing and Information Systems
(ICICIS 2002), Cairo, Egypt, June 24-26, 2002
Configware / Software Co-Design: Be Prepared For the
Next Revolution! - 5th IEEE Workshop on Design & Diagnosis of Electronic
Circuits & Systems (DDECS'02), Brno, Czech Republic, April 17 - 19,
2002
Reconfigurable Computing Architectures
and Methodologies for System-on-Chip; 3rd Workshop.on Enabling
Technologies for System-on-Chip Development (SoC 2001),
November 19-20, 2001, Tampere, Finland.
Reconfigurable Computing: a
New Business Model - and its Impact on SoC Design; DSD'2001 EUROMICRO Symposium
on Digital Systems Design, Warzaw, Poland, Sept. 4 - 6, 2001
Next Generation Configware merging
Prototype and Product; International Workshop on Rapid System Prototyping,
RSP'98, Leuven, Belgium, June 3 - 5, 1998
How to Survive a Possible New
Design Crisis; IFIP WG10.1 & 10.7 Workshop, University of Sterling,
UK, July 2-4, 1997
Custom Computing Machines -
an overview; Workshop on Design Methodologies for Microelectronics, DMM'95,
Smolenice Castle, Czech Republic, Sept. 1995
VLSI - from Evolution to Revolution;
1979 Int'l. Symposium on Microcomputers, Budapest, Hungary, Oct. 1979
Impact and Education of the
'New Microelectronics'.; 25 Year Anniversary Symposium of the Institute
for Imformation Processing (founded by Karl Steinbuch), University of Karlsruhe,
11. March 1983´
Introduction to VLSI-System
Design, E.I.S. Summer School "CAD/VLSI", Arnoldsheim/Taunus, Germany, Juni
1986
Invited
Papers
Data-Stream-Based Computing: Models and Architectural
Resources; International Conference on
Microelectronics, Devices and Materials (MIDEM
2003), Ptuj, Slovenia, Oct.1-3, 2003
Toward Reconfigurable Computing via Concussive Paradigm
Shifts; (Anniversary Colloquium at Prof. Glesner's 60th Birthday;
August 29, 2003, Darmstadt, Germany) to appear in "ti"
Trends in Reconfigurable Logic and Reconfigurable
Computing; 9th IEEE International Conference on Electronics, Circuits and
Systems - ICECS 2002, September 15-18, 2002, Dubrovnik, Croatia
(together wirh M. Herz (Agilent Technologies), M.
Miranda, E. Brockmeyer (IMEC, Leuven, Belgium), F. Catthoor (IMEC and K.U.Leuven,
Belgium): Memory Organisation for Stream-based Reconfigurable Computing;
9th IEEE International Conference on Electronics, Circuits and Systems
- ICECS 2002, September 15-18, 2002, Dubrovnik, Croatia
Reconfigurable Computing - Architectures
and Methodologies for System-on-Chip; SoC technology seminar "Enabling
Technologies for System-on-Chip Development"; Tampere, Finland,
November 19-20, 2001,
Reconfigurable Computing: the
Roadmap to a New Business Model - and its Impact on SoC Design; SBCCI 2001
- 15th Symposium on Integrated Circuits and Systems Design, Brasilia,
DF, Brazil, September 10-15, 2001
(invited embedded tutorial)
Coarse Grain Reconfigurable Architectures; Asian and South Pacific Design
Automation Conference and Exhibit (ASP-DAC 2001), Yokohama, Japan,
January 30 - Febr. 2, 2001
Makimoto's Law, the 2nd Design
Crisis, and the Future of Reconfigurable Computing; Int'l.
Seminar on Dynamically Reconfigurable Architectures; Schloss Dagstuhl,
Germany, June 25-30 2000 -
Reconfigurable Computing; Kongress
Highly Reliable Hard- and Software Systems 1999 (HighSys '99), Sindelfingen,
Oktober 1999
Freedoms and Necessities in
the Knowlege Society; Freiheiten und Zwaenge in der Wissensgesellschaft
("talk by the fireside"); Annual Symposium of the "Drawing the balance
of middle class exonomy politics" Association for studies of middle
class economy (Studiengesellschaft fuer Mittelstandsfragen),
Inzell, Bavaria, Germany. October 1998
On the Application of the KressArray
to Rapid Prototyping; Design, Automation and Test in Europe Conference,
DATE'98, Paris, France, February 23 - 26, 1998
The Microprocessor is no more
General Purpose: why Future Reconfigurable Platforms will win; International
Conference on Innovative Systems in Silicon, ISIS'97, Austin, Texas,
USA, October 8-10, 1997
A General Approach in System
Design Integrating Reconfigurable Accelerators; International Conference
on Innovative Systems in Silicon; Austin, Texas, USA, October 9-11, 1996
Xputer: ASIC or Standard Circuit?;
Microelectronics Symposium of the German Association for Microelectronics
(GME), Oct. 08. - 10, 1993, Dresden, Germany
KARL and ABL; (Invited Paper),
NATO Advanced Study Institute on Fundamentals and Standards in Hardware
Description Languages, 16. - 26.04.93, Il Ciocco, Barga, Italy, 1993
The
Role of Hardware Description Languages in Integrated CAD Systems for VLSI
Design (invited paper); CVT Open Workshop; CNET (Centre National
d'Etudes de Telecommunication), Meylan (Grenoble), Frankreich, April 1986
Shared
Culture: CIF Library, Starting Frames, Scalable Design Rules; NATO Advanced.
Study Institute on Design Methodologies for VLSI Circuits, Louvain-la-Neuve,
Belgium, 8. - 18. July. 1980
Basics
of Structured Design Methodologies: Data Path and Finite State Machines;
NATO Advanced. Study Institute on Design Methodologies for VLSI Circuits,
Louvain-la-Neuve, Belgium, 8. - 18. July. 1980
Y. Chu, R. Hartenstein, G.
J. Lipovski et al.: Why do we need Hardware Description Languages; IEEE
COMPUTER, December 1974
On the Interpretive Mechanism of Microprogrammed Systems;
EUROMICRO workshop, Paris, France, 10. - 11. June. 1974
Papers in Books and Archival
Journals
R. Hartenstein, J. Becker, K. Schmidt, M. Weber (invited
paper): High-Performance Computing Using a Reconfigurable Accelerator;
CPE Journal, Special Issue of Concurrency: Practice and Experience, John
Wiley & Sons Ltd., New York, 1996
R. Hartenstein, A.G. Hirschbiel, M. Riedmueller,
K. Schmidt, M.Weber (invited reprint): A Novel ASIC Design Method based
on a Machine Paradigm; IEEE-JSSC - Journal of Solid State Circuits , Vol.
26, No. 7 (July 1991), pp. 975-989,
R. Hartenstein, A.G. Hirschbiel, M.Weber (invited
reprint): A Novel Paradigm of Parallel Computation and its Use to
Implement Simple High Performance Hardware; Future Generation Computer
Systems (North Holland) 7, 1991/92, p. 181-198,
R. Hartenstein: KARL and ABL, in (J. P. Mermet, editor):
Fundamentals and Standards in Hardware Description Languages; Kluwer
Academic Publishers, Dordrecht / Boston, 1993, pp. 447-466,
A. Ast, R. Hartenstein et al.: High Performance VLSI
Signal Processing; in:: M. Bayoumi (editor): VLSI Image and Signal Processing;
Kluwer Academic Publishers, Dordrecht / Boston, 1992.
R. Hartenstein: A. Hirschbiel, M.Weber: MOM - Map
oriented Machine; in: Ambler, Agrawal, Moore (editors): Hardware Accelerators,
Adam Hilger, Bristol / Boston, 1988
R. Hartenstein, A. Hirschbiel, M. Weber: MOM - Map
Oriented Machine; in: E. Chiricozzi, A. D'Amico (editors): Parallel Processing
and Applications; Amsterdam / New York, North Holland Publishing Co, 1988
R. Hartenstein: Introduction; in: (R. Hartenstein,
editor): Advances in CAD for VLSI, Vol. 7: Hardware Description Languages;
Amsterdam / New York, North Holland / American Elsevier, 1986, pp.
3-12
R. Hartenstein: The Classification of Hardware Description
Languages; in: (R. Hartenstein, editor): Advances in CAD for VLSI, Vol.
7: Hardware Description Languages; Amsterdam / New York, North Holland
/ American Elsevier, 1986, pp. 15-47
R. Hartenstein, U. Welters: RT level CAD tools
and simulation, in: G. Fichtner, M. Morf (editors): VLSI Tools and Applications,
Kluwer Academic Publishers, Dordrecht / Boston, 1986
Refereed Papers in Conference Proceedings
(embedded tutorial) A Decade
of Reconfigurable Computing - a Visionary Retrospective; Int'l Conf. and
Exhibit on Design, Automation and Test in Europe (DATE 2001); Munich, Germany,
March 13 - 16, 2001
Interfacing the MoM-PDA
to an Internet-based Development System; 32th Annual Hawaii Int'l Conf.
on System Science (HICSS-32), Hawaii, USA, January 5 - 8,1999
A Revival of Systolic Arrays
by Course Granularity Reconfigurable Circuits, Seminar on Dynamically Reconfigurable
Architectures, Schloss Dagstuhl, Germany, February 22 - 27, 1998
Parallelization in Co-Compilation
for Configurable Accelerators; Asia and South Pacific Design Automation
Conference, ASP-DACÕ98, Yokohama, Japan, Feb. 10-13, 1998
An Innovative Platform for Embedded
System Design ; Workshop Zielarchitekturen Eingebetteter Systeme, ZES'97,
in conjunction with the Fachtagung Architekturen von Rechensystemen ARCS'97,
Rostock, Germany, September 11, 1997
An Embedded Accelerator for
Real World Computing; IFIP International Conference on Very Large Scale
Integration, VLSI'97, Gramado, Brazil, August 26-29, 1997
A Two-level Co-Design Framework
for data-driven Xputer-based Accelerators; 30th Annual Hawaii Int. Conf.
on System Science (HICSS-30), January 7-10, Wailea, Maui, Hawaii, USA,
1997.
Co-Design and High Performance
Computing: Scenes and Crisis; Reconfigurable Technology for Rapid Product
Development & Computing, Part of SPIE International Symposium '96,
Boston, USA, Nov. 1996
A Synthesis System for Bus-based
Wavefront Array Architectures; ASAP 96 Application Specific Array Processors,
Chicago, USA, August 1996
Two-Level Hardware/Software
Partitioning Using CoDe-X; Int. IEEE Symp. on Engineering of Computer Based
Systems (ECBS), Friedrichshafen, Germany, March 1996
Two-Level Partitioning of Image
Processing Algorithms for the Parallel Map-oriented Machine; 4th Int. Workshop
on Hardware/Software Co-Design CODES/CASHE '96, Pittsburgh, USA, March
1996
CoDe-X: A Novel Two-Level Hardware/Software
Co-Design Framework; VLSI Design 96 Conf., Bangalore, India, January 1996
CoDe-X: A Novel Two-Level Hardware/Software
Co-Design Framework; Proc. 9th International Conference on VLSI Design,
Bangalore, India, Jan. 1996
A Reconfigurable Parallel Architecture
to Accelerate Scientific Computation; International Conference on High
Performance Computing, New Delhi, India, Dec. 1995
Data-procedural Languages for
FPL-based Machines; 4th Int. Workshop On Field Programmable Logic And Applications,
FPLÕ94, Prague, September 7-10, 1994
Parallelizing Compilation for
a Novel Data-Parallel Architecture; PCAT-94, Parallel Computing: Technology
and Practice, Wollongong, Australia, Nov. 1994
CASHE, Using a New Machine Paradigm;
Workshop Codes/CASHE´93, 24. - 27.05.93, Igls, Innsbruck, Austria,
1993
Hardware/Software Co-Design;
3rd International Workshop on Field Programmable Logic and Applications,
07. - 10.09.93, Oxford, England, 1993
MoPL-3: A New High Level Xputer
Programming Language; 3rd International Workshop on Field Programmable
Logic and Applications, 07. - 10.09.93, Oxford, England, 1993
A Novel High-performance Machine
Paradigm and ASIC Design Methodology; International Design Automation Workshop
("Russian Workshop"), 29. - 30. 06. 92, Moskau, Russia, 1992
Novel High Performance Machine
Paradigms and Fast-Turnaround ASIC Design Methods: a Consequence of, and
a Challenge to, Field-programmable Logic ; 2nd International Workshop on
Field-Programmable Logic and Applications, 31. 08. - 02. 09. 92, Vienna
University of Technology, Vienna, Austria, 1992
A High Performance Machine Paradigm
Based on Auto-Sequencing Data Memory; HICSS-24 Hawaii International Conference
on System Sciences, Koloa Hawaii, January 1991
Xputer: Neuartige Hochleistungsprozessoren,
deren Prinzipien und Realisierungen; University of Stuttgart, Germany,
Jan. 1991
Xputer use for Acceleration
of Neuronal Network Simulation; 3rd Int. Workshop on Adaptive Learning
and Neuronal Networks, Schloss Reisensburg, Germany, 2.-7.7 1991
A Technology Adaptable Device
Generator as a Frontend for Layout Generators, EDAC '90 - European Design
Automation Conference, Glasgow, UK, March 1990
Xputers - An Open Family of
Non von Neumann Architectures, ITG/GI-Konferenenz ueber die Architektur
von Rechensystemen, Munich, March 5. - 7, 1990
Using Xputers as Inexpensive
Universal Accelerators in Digital Signal Processing; Bilkent '90 International
Conference on New Trends in Communication, Control and Signal Processing,
Ankara, Turkey, Juli 1990
The Machine Paradigm of Xputers
and its Application to Digital Signal Processing Acceleration, International
Conference on Parallel Processing, St. Charles, Illinois, August 1990
A Novel Paradigm of Parallel
Computation and its Use to Implement Simple High Performance Hardware;
Internationale Konferenzen CONPAR '90 und VAPP IV, Zurich, Schweiz, September
1990
Extremely Efficient Array Emulation
by a Computational Device using Innovative Machine Principles; ASICS Open
Workshop on Regular Array Architectures, Patras, Greece, 24. September
1990
A Novel Paradigm of Parallel
Computation and its Use to Implement Simple High Performance Hardware,
InfoJapan '90, Tokio, Japan, October 1990
Mapping Systolic Arrays onto
the Map-Oriented Machine (MoM); International Workshop on Systolic Arrays,
Killarney, Mai 1989
SYS3 - A CHDL-Based Systolic
Synthesis System; IFIP Int'l Symposium on Hardware #descriptive Languages
1989 (CHDL '89), Washington, D.C. June 1989
A Pseudo Parallel Architecture
for Systolic Algorithms; IFIP Workshop on Parallel Architectures in Silicon,
Grenoble, December 1989
Some new features in KARL-4
and superKARL - a survey; 2nd ABAKUS Workshop, Innsbruck, Austria, 4. -
7.9.1988
Integration of Simulation, Test
Development and Test in a High Level Design Environment; IFIP TC10 Working
Conference on VLSI Architecture, Pisa, Italien, 20. - 22.09.1988
Computer Structure Partitioning
Schemes; IFIP TC10 Working Conference on VLSI Architecture, Pisa, Italy,
20. - 22.09.1988
Design for Testability by Integration
of Functional Simulation and Test Pattern Development; NTG workshop (Nachrichtentechnische
Gesellschaft, Stuttgart, 1986
Future Work on KARL and related
CAD Tools; ABAKUS Workshop, Passau, Germany, June 1986
ABLED - ein CAD Tool for Designingn
Digital Systems*, Proc. DECUS Muenchen Symposium, Stuttgart, Germany, 1986
Higher Level Simulation and
CHDLs; IFIP Summer School on VLSI Design; Beatenberg, Switzerland, 1986
CAD Tools for Experimenting
with Alternative VLSI Architectures; IFIP Workshop on VLSI Architectural
Design; Torino, Italy, 1986
Map-Oriented Processing: Accelerator
concept and VLSI design environment for a class of data processing problems;
Seminar*, IMS, Fraunhofer-Institute for Microelectronic Systems, Duisburg,
Germany, July 1986
Towards Engineering System Sciences;
Annual Symposium of SEFI (Societé Européenne de Formation
des Ingenieurs), Madrid, Spane, Sept. 1985
Towards Engineering System Sciences.,
GI Conference on Modeling digital Systems, Bernried, Starnberger See, Germany,
June 24. - 25, 1982
Towards the personal CAD station;
Mikroelektronics Congress, Munich, Germany, Nov. 1982
KARL as an interpretive graphic
input to VLSI CAD tools; 2nd Int'l. Symposium on Computer Hardware Descriptions
Languages and their Applications (CHDL), Palo Alto, Oct. 1979
A Computer for the Hardware
Description Language KARL; Annual Conference of the GI (Gesellschaft fuer
Informatik), Berlin, Sept. 1978
Generalized Principles of Microprogrammable
Computer Structures*; Annual Conference of the GI (Gesellschaft fuer Informatik),
Berlin, Sept. 1978
Hierarchy of Interpreters for
Modelling Complex Digital Systems; Colloquium, Annual Conference
of the GI (Gesellschaft fuer Informatik), Hamburg, Oct. 8 - 10, 1973
On the Use of KARL for
Description and Design of Hardware for MSI or LSI Chips; 2nd Int'l. Symposium
on Computer Hardware Descriptions Languages and their Applications (CHDL),
Darmstadt, Germany, July 31. - Aug 1, 1974
The Use of ABL for Design and
Description of Hardware Structures; IFIP 2nd Int'l. Symposium on Computer
Hardware Descriptions Languages and their Applications (CHDL), Darmstadt,
Germany, 31. July. - 1. Aug. 1974
Microprogramming Concepts -
A Step towards Structured Hardware Design; 7th ann. Symposium on Mircoprogramming
(MICRO'74), Palo Alto, 29. Sept. - 2. Oct. 1974
Concepts of Microprogramming
; GI-NTG-Conference 'Structure and Operation of Computers',
Braunschweig , Germany, 20. - 22. March. 1974
Increased Hardware Complexity
- A Challenge to Computer Science Education; 1st Int'l. Symposium
for Computer Architecture (ISCA), Gainesville, Florida, Dec. 9. - 11, 1973
A special Machine System for
Visual Pattern Recognition (H. Kazmierczak, F. Holdermann, speaker: R.
Hartenstein); AGARD-Bionics-Symposium, Brussels, Belgium, Sept. 1968
Non-refereed Papers in Newsletters etc.
R. Hartenstein: Wiring Algebra
for Specification of VLSI Design Problems; SIGDA Newsletter, Aug. 1980
R. Hartenstein: The use of KARL
for the description of Integrated Circuits; iin: R. Piloty (editor):
Proceedings of the Intl. Workshop on Computer Hardware Description Languages,
Darmstadt, 1974, ACM Lecture Notes, German Chapter ACM 1975
R. Hartenstein: The use of the
block diagram language ABL; in: R. Piloty (editor): Proceedings of the
Intl. Workshop on Computer Hardware Description Languages, Darmstadt, 1974,
ACM Lecture Notes, German Chapter of the ACM 1975
R. Hartenstein: Hierarchy of
Levels within Computer Architecture; CAN - Computer Architecture News,
vol. 3, Nr. 1, 1974
R. Hartenstein: Towards a Language
for the Description of IC Chips; SIGMICRO Newsletter .vol. 4, no. 4, 1973
R. Hartenstein: A Halfbaked
Idea on a set of Register Transfer Primitives; SIGMICRO Newsletter vol.
4, no. 3, 1973
R. Hartenstein, K.-D.
Mueller-Glaser: A Microprogrammable Display Processor for 3-dimensional
Interactive Computergraphics; SIGMICRO Newsletter vol. 4, no. 2, 1973
Technical
Reports and Lecture Notes, etc. (published,
or internal)
R. Hartenstein, A. Ast,
J. Becker, et al.: Data-procedural Languages for FPL-based Machines; University
of Kaiserslautern, Fachbereich Informatik, Internal report no. 264/95,
1995
R. Hartenstein: Hardware/Software
Codesign; Internal Report No. 246/94, University of Kaiserslautern, 1994.
R. Hartenstein: The History
of KARL and ABL; (Internal report no Nr. 232/93), Fachbereich Informatik,
University of Kaiserslautern, April 1993
R. Hartenstein, S. Perdomo,
A. Nuñez, et al.: Report on Interconnect Modelling: Second Periodic
Progress Report, PATMOS Projekt, University of Kaiserslautern, Dezember
1991
R. Hartenstein, M. Riedmueller,
K. Schmitt, M. Weber: A Novel Asic Design Approach Basd on a New
Machine Paradigm; Internal report no. 212/91, University of Kaiserslautern,
Fachbereich Informatik, Juli 1991
R. Hartenstein, J. Bloedel:
Report on Extraction: Second Periodic Progress Report, PATMOS Project,
University of Kaiserslautern, December 1991
R. Hartenstein,
J. Bloedel, D. Schroeder, W. Wilkes*: DASSY - Survey on Information Models;
Milestone meeting report M3; DASSY Project; July 23, 1991
R. Hartenstein, J. Bloedel,
M. Brandstetter, W. Drangmeister, D. Schroeder: Device Descriptions, EDIF
Version 205, Proposal No. DM&V-3 Version 1.0; Internal report no. 211/91,
Fachbereich Informatik, University of Kaiserslautern, May 31, 1991
R. Hartenstein, J. Bloedel:
Parameterized Topological Device Descriptions, Proposal for EDIF Version
2 0 5, Version 1.0, Report DASSY Project, University of Kaiserslautern,
January 1991
R. Hartenstein, A. G. Hirschbiel,
M. Riedmueller, K. Schmidt, M. Weber: A Novel Paradigm of Parallel
Computation and its Use to Implement Simple High Performance Hardware;
internal report, University of Kaiserslautern 1990
R. Hartenstein, J. Bloedel:
Topological Device Descripiton for EDIF; Report EDIF Device Modeling &
Verification; IEEE EDIF Standardization Committee, TSC (Technical Subcommittee)
on Technology, August 1990
R. Hartenstein, J. Bloedel
et. al.: General Unit Definition for EDIF; EDIF Device Modeling & Verification
TSC (Technical Subcommittee), Proposal DM&V No. 1, May 1990
R. Hartenstein, A. Ast,
J. Bloedel, U. Jasnoch, J. Reedmer, M. Ungerer*: Concept of a Procedural
Tool Interface within DASSY Prototypes; DASSY project report, University
of Kaiserslautern, 1990
R. Hartenstein, A. Ast,
J. Bloedel et. al.*: Tool Interface Requirements from the Tools' Point
of View; DASSY project report, GMD Gesellschaft fuer Mathematik
und Datenverarbeitung, St. Augustin, March 1990
R. Hartenstein, A. Ast,
J. Bloedel: Configuration Data for fault-model independent Automatic Test
Generators; DASSY project report, University of Kaiserslautern, Fachbereich
fuer Informatik, March 1990
R. Hartenstein, A. Ast,
J. Bloedel*: Tool Interface Requirements for Test Generators and #digital
Simulators at RT Level, DASSY project report, University of Kaiserslautern,
Fachbereich fuer Informatik, March 1990
R. Hartenstein, A. Ast,
J. Bloedel: Technology Data for Circuit Extraction and Layout Synthesis:
DASSY project report, University of Kaiserslautern, March 1990
R. Hartenstein, A. Ast,
P. Bittner, J. Bloedel, M. Weber, U. Zahm*: Anforderungen an die
WZ Interface Requirements from the Tool's Point of View: DASSY project
report University of Kaiserslautern, Fachbereich fuer Informatik,
February 1990
R. Hartenstein, R. Hauck:
CVS_BK Language Reference Manual; CVS-Bericht; CSELT, Torino (Italy)
/ University of Kaiserslautern, 1989
R. Hartenstein, A. Hirschbiel,
M.Weber: MOM - Map Oriented Machine - An Innovative Computing Architecture;
Internal report no. 181 / 88, Fachbereich Informatik, University of Kaiserslautern,
1987
R. Hartenstein, J. Bloedel,
W.Nebel, M.Ryba*: Automatic Extraction of RT level Functional Descriptions
from Layout of Integrated Circuits; Internal report no. 180 / 88, Fachbereich
Informatik, University of Kaiserslautern, 1987
R. Hartenstein, J. Bloedel,
W. Nebel, M. Ryba: EDIF Notation for Layout / Circuit Relations; Interner
Bericht Nr. 179 / 88, Fachbereich Informatik, Univ. Kaiserslautern, 1987
R. Hartenstein, G. Alfs:
Design and Implementation of a Heuristic Search Algorithm for the KARATE
System; Internal report no. 183 / 88, Fachbereich Informatik, University
of Kaiserslautern, 1987
R. Hartenstein, R. Heinen*:
User Manual for KARL-3 on ATARI-ST; report, Fachbereich Informatik,
University of Kaiserslautern, 1987
R. Hartenstein, R. Hauck,
K. Lemmert, A. Wodtko: KARL-4 and SCIL-3 Grammar (Draft); ESPRIT /
CVS report, Dept. of Computer Science, University of Kaiserslautern, July
1987
R. Hartenstein, R. Hauck:
A Behavioural / Non-procedural Mixed-Level Simulator for Digital VLSI Systems;
ESPRIT report, CS Dept., Univ. Kaiserslautern, Febr. 1987
R. Hartenstein, R. Hauck:
Simulator Specification for CVS_BK; ESPRIT/ CVS report, Informatics Dept.,
University of Kaiserslautern, Febr. 1987
R. Hartenstein: Proposal of
a High Level Hardware Description Language; ESPRIT / CVS report, Informatics
Dept., University of Kaiserslautern, Sept. 1986
R. Hartenstein: Entwurf eines
Universalprozessors mit Hocharchitektur, University of Kaiserslautern,
1986
R. Hartenstein, A. Bonomo,
G. Girardi, L. Lavagno, R.Hauck: Semantic Specification of CVS_BK Language
(CVS Behavioural Karl); ESPRIT / CVS report, CSELT, Torino, Italy / Informatics
Dept., University of Kaiserslautern, Germany, Febr. 1987
R. Hartenstein, A. Bonomo, G.
Girardi, L. Lavagno, R. Hauck: Syntax Diagrams of the CVS_BK Language (CVS
Behavioural Karl); ESPRIT / CVS report, CSELT, Torino, Italy / Informatics
Dept., Univ. Kaiserslautern, Germany, Febr. 1987
R. Hartenstein: Technische Informatik
II, Skriptum zur Vorlesung, Fachbereich fuer Informatik, University of
Kaiserslautern, 1987
R. Hartenstein, R. Hauck,
A. Hirschbiel:: A KARL simulator Physical Model Extension; report, University
of Kaiserslautern, 1986
R. Hartenstein, R. Hauck:
Recursive Cell Declarations in a RT Language; report, University of Kaiserslautern,
1986
R. Hartenstein, R. Hauck:
A simple Silicon Synthesizer for MOL circuits; report, University of Kaiserslautern,
1986
R. Hartenstein, R. Hauck:
Extracting Functional Descriptions from Matrix-orientierted
Layout; report, Univ. of Kaiserslautern, 1986
R. Hartenstein, W. Nebel:
REX: a new CAD Tool shifts Functional Circuit Verification towards RT
level; report, University of Kaiserslautern, 1986
R. Hartenstein, R. Hauck)
Design of Symbolic Layout using RT Level CAD Tools; report, University
of Kaiserslautern 1986
R. Hartenstein, K. Lemmert,
A. Wodtko: KARL-III Language Reference, second edition (completely rewritten),
University of Kaiserslautern, March 1986
R. Hartenstein, W. Nebel:
EDIF-based Notation for Layout/Circuit Relations: toward Technnology-Independance
of CAD Tools; report; University of Kaiserslautern 1985
R. Hartenstein, A. Wodtko:
Functional Test Generation within the KARL-III System; report, University
of Kaiserslautern 1985
R. Hartenstein, G. Alfs,
A. Wodtko: C-Testable Cells for ATPG from RT Descriptions; report;
University of Kaiserslautern 1985
R. Hartenstein, K. Lemmert:
The Hardware Description Language KARL-III: its Integration into a
CAD Tool Box; report, University of Kaiserslautern 1985
R. Hartenstein, R. Hauck:
KARL language update, CVT report, University of Kaiserslautern,1985
R. Hartenstein: KARL-III Primer
(draft), CVT report, University of Kaiserslautern, April 1985
R. Hartenstein, G. Girardi:
ABLED - a RT Level Schematic Editor and Simulator Unser Interface; CVT
report; CSELT Torino, Italy / University of Kaiserslautern 1985
R. Hartenstein: Kaiserslauterns
CAD Activities within the CVT Project; interner Bericht 125/85, Fachbereich
Informatik, University of Kaiserslautern, 1985
R. Hartenstein, A. Wodtko: Automatic
Generation of Functional Test Patterns from RT Language Source; Interner
Bericht; University of Kaiserslautern, March 1985
R. Hartenstein, R. Hauck, A.
Hirschbiel, W.Nebel, M.Weber: PISA - A CAD package and special hardware
for pixel-oriented layout analysis, ICCAD, Santa Clara, 1984, IEEE, New
York 1984
R. Hartenstein, J. Bloedel,
R. Hauck, M. Ryba, H.Salzmann, M.Weber: PISA user manual; report, Kaiserslautern
1985
R. Hartenstein,
B. Borrmann: superKARL-III Specification; CVT report, University of Kaiserslautern,
1984
R. Hartenstein, B. Borrmann*:
Translation of superKarl Constructs into the Computer Hardware Descriptive
Language KARL; report, Univ. of Kaiserslautern, May 1984
R. Hartenstein, K. Lemmert:
KARL-III reference manual; CVT report, University of Kaiserslautern 1984
R. Hartenstein, G. Girardi:
ABL-Specification -Draft-; CVT-report, Torino, Italy / University of Kaiserslautern,
1983
R. Hartenstein: KARL-II application
notes; CVT- report; University of Kaiserslautern, 1983
R. Hartenstein: Specification
of the KARL-III language; CVT report; University of Kaiserslautern, 1983
R. Hartenstein, A. Mavridis:
RTCode Instant; CVT report, University of Kaiserslautern, 1983
R. Hartenstein, P. Liell:
KARL-II Language Reference Manual, report, University of Kaiserslautern
1983
R. Hartenstein, P. Liell:
Specification of the KARL-III language ; University of Kaiserslautern,
June 1983
R. Hartenstein, P. Liell,
E. Schaaf, B. Weber: KARL user manual and introduction; report, University
of Kaiserslautern, 1981
R. Hartenstein,. P. Liell, E.
Schaaf: The Grammar of KARL 2; report, University of Kaiserslautern 1981
R. Hartenstein, P. Liell,
E. Schaaf, B. Weber: CHARLES - A Register Transfer Language for Hardware
Design and Specification, report, Univ. Kaiserslautern, 1981
R. Hartenstein, H. Bellm**,
J. Diekmann, M. Floetotto, W. Konrad, A. Sauer**, W. Schmitter**: Implementation
of the ESRA Computer Network Kit: an Approach toward a Methodology for
Reliable Software*; report, 1980
R. Hartenstein*: Innovation
Cycles in VLSI-Technology; internal report, Univ. of Kaiserslautern 1980
R. Hartenstein*: Curricular
Considerations on the Role of Hardware in Computer Science; internal report,
University of Kaiserslautern, 1980
R. Hartenstein*, E. von
Puttkamer: Is Informatics an Engineering Science?; (manuscript, submitted
to and withdrawn from GI Informatik Spektrum), Kaiserslautern, Germany,
1980
R. Hartenstein, J. Dieckmann:
Local Micro Network to support Software Modularity; report, FB Informatik,
University of Kaiserslautern, 1980
R. Hartenstein: Memo on VLSI
research and developement funding; Univ. Kaiserslautern, 1979
R. Hartenstein, P. Liell,
E. Schaaf, B. Weber: The grammar of KARL-2; University of Kaiserslautern
1979
R. Hartenstein: KARL - The Karlsruhe
Architectural
and Register Transfer Language - A draft specification; course
handout, Informatics Department, University of Karlsruhe, 1974
R. Hartenstein: Introduction
to formal descriptions in Computer Organisation; internal report, University
of Karlsruhe, 1974
R. Hartenstein*: Computer Architecture
and Microprogramming; course handout, University of Karlsruhe, 1973
R. Hartenstein*: Foundations
and User Instructions of the Lab course ´Technische Informatik´;
Institute for Informatik IV, University of Karlsruhe, 1972
R. Hartenstein*: Concept of
an advanced lab course in computer structures; internal report, Institut
fuer Informatik IV, University of Karlsruhe, 1972
R. Hartenstein*: Foundations
of the Lab Course Set-up ´Microprogramming´; Kapitel zum Skript
des Praktikums Technische Informatik, Inst. f. Informatik IV, Univ. Karlsruhe
1971
R. Hartenstein*: Automatic Logic
Tester, internal report, Informatik IV, Univ. Karlsruhe, 1971
R. Hartenstein*: Foundations
of the Lab Course Set-up 'Feedback Switching Networks'; Chapter ot the
handout for the Lab course "Technische Informatik", Inst. f. Informatik
IV, Univ. Karlsruhe, 1971
R. Hartenstein*: On the Synthesis
of Finite State Machines; in: annual report 1970 of the Institute for Information
Processing, University of Karlsruhe, 1970
R. Hartenstein*: FSM Synthesis
for pattern processing and classification; Chapter in Research Report
Automatic Imaga Analysis and Character Recognition, (editor: H. Kazmierczak),
Univ. Karlsruhe, 1969
R. Hartenstein*: FSM Synthesis
from Regular Expressions and their Application to Character Recognition;
handout manuscript, Seminar, Institute for Information Processing, Univ.
Karlsruhe, 1968
R. Hartenstein*: FSM Application
in Pattern Recofnition; chapter in annual report 1968 of the Institute
for Information Processing, Uni. Karlsruhe, 1968
R. Hartenstein,
H. Kazmierczak, F. Holdermann*: Automatic Classifier Synthesis; in: annual
report of the Institute for Information Processing, Universit of Karlsruhe
1967
R. Hartenstein*: The PATTERN
HANDLING Software Package; internal report, Research group on Automatic
Character Recognition, Institute for Information Processing, University
of Karlsruhe 1967
R. Hartenstein, P. Grube*r:
A Controller for Punched Tape I/O usnig a Tally 420 PR and an electronic
Typewriter IBM 73/BCD; report KFK 316, Nuclear Research Center, Karlsruhe,
March 1965
R. Hartenstein,
W. Juengst*: A flexible electronic Data Aquisition Kit for Experiments
in Nuclear Physics; report KFK 275, Nuclear Research Center, Karlsruhe,
December 1964
R. Hartenstein*: Modified Controller
for Tally-Tape Punch Drive 420 PR; report KFK 245, Nuclear Research
Center, Karlsruhe, August 1964
R. Hartenstein, U. Jochimsen*:
Controller for Puched Tape Output by 1-D and 2-D organized Scanning of
Data Sources; report KFK 201, Nuclear Research Center, Karlsruhe, January
1964
Popular
or Political Papers
R. Hartenstein*: Competitiveness
should be Primary Goal of our Education System; WELT am SONNTAG,
19. 5. 1996
R. Hartenstein*: Punchy Innovation
Forces decide the Competition of Nations; WELT am SONNTAG, 12. 5.
1996
R. Hartenstein*: Knowlege is
the new Fuel of Wealth and Labour ; WELT am SONNTAG, 5. 5.
1996
R. Hartenstein*: Our Society
has no Fancy on High Tech; DIE WELT, 19. Feb. 1996
R. Hartenstein*: The Microelectronics
Market and new Infrastructures; VDI-Nachrichten, 29. August 1986
R. Hartenstein* (editorial):
Outbreak of the E.I.S. age; Computer Magazin 3 (March) 1986
R. Hartenstein*: Germany in
the Role of a Developing Country; WELT am SONNTAG, 1983
R. Hartenstein*: AUF EIN WORT;
DIE WELT, 24. Okt. 1983
R. Hartenstein*: AUF EIN WORT;
DIE WELT, 13. Mai 1982
R. Hartenstein*: AUF EIN WORT;
DIE WELT, 07. Jan. 1981
R. Hartenstein*: AUF EIN WORT;
DIE WELT, 11. Dez. 1980
R. Hartenstein*: AUF EIN WORT;
DIE WELT, 16. Okt. 1980
R. Hartenstein*, K. Steinbuch:
The Fourth Industrial Revolution; Techniken der Zukunft 3, Nov. 1971
R. Hartenstein*, K. Steinbuch:
The Fourth Industrial Revolution; Rank Xerox Magazin 1 / 1971
R. Hartenstein*: Management
Information with Computer and Display; Techniken der Zukunft 2, Juni
1971
R. Hartenstein*, K. Steinbuch:
Information - yesterday, now, and tomorrow; Messe-Magazin (Rank Xerox),
April 1971
R. Hartenstein*: Database Systems
are coming; DIE WELT, 19. 6. 1971
R. Hartenstein, K. Steinbuch*:
Future Aspects of Information Technology; Techniken der Zukunft, Vol. 1,
Januar 1971
_______________
*) in German language
**) Siemens AG, Munich,
Germany
