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Technical Presentations
(categorized)
by Reiner W. Hartenstein
University of Kaiserslautern
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Contents of this page Links
Keynotes
Documented Invited Presentations
Awards etc.
Invited Presentations in International
   Company Meetings
Invited Courses given
Other Invited Presentations
Contributions as a Panelist
Refereed Documented Presentations
Bio incl E.I.S. | detailed bio | short bio
Technical Presentations
Talks cumulative
Recent papers and talks
Papers and Books, categorized
Papers cumulative | books
Theses directed
Version with Alumni Prof links
Theses directed: with alumni links
Advisory Activities
Serving Conferences and Journals
Serving Professional Organizations

History of KARL | KARL users
History of E.I.S. | KARL-related quotation index

Technical Presentations
(last update: October 2004)

Keynotes (documented)

  1. see   http://hartenstein.de/keynotes.htm

Documented Invited Presentations  (last update: October 2004)

  1. The Digital Divide of Computing; 2004 ACM International Conference on Computing Frontiers (CF04); April, 14-18, 2004. Ischia, Italy,   

  2. Morphware: neue Perspektiven für eingebettete Systeme; Selbstoptimierende Systeme des Maschinenbau: Workshop Selbstoptimierung und Adaption, Paderborn, Germany, 24. - 25. November 2003 

  3. Data-Stream-Based Computing: Models and Architectural Resources; International Conference on Microelectronics, Devices and Materials (MIDEM 2003), Ptuj, Slovenia, Oct.1-3, 2003

  4. Reconfigurable Computing and its Enabling Technologies -- for the Personal Supercomputer (PS) to replace the PC; THALES internal workshop; September 18, 2003, Orsay, France  

  5. Toward Reconfigurable Computing via Concussive Paradigm Shifts; Anniversary Colloquium at Prof. Glesner's 60th Birthday;  August 29, 2003, Darmstadt, Germany.

  6. Data-Stream-Based Computing: Models and Architectural Resources; International Conference on Microelectronics, Devices and Materials (MIDEM 2003), Ptuj, Slovenia, Oct.1-3, 2003 

  7. Toward Reconfigurable Computing via Concussive Paradigm Shifts;  Anniversary Colloquium at Prof. Glesner's 60th Birthday;  August 29, 2003, Darmstadt, Germany - publ. by special issue of "it"

  8. Reconfigurable Computing and its Impact; Reconfigurable Computing and Communication Workshop, Hillsboro, Oregon, USA, May 15-16, 2003
  9. Datastream-based Reconfigurable Computing;  Dresdner Arbeitstagung Schaltungs- und Systementwurf (Workshop on Circuit and Systems Design - DASS´2003), in conjunction with  rhe Workshop System Design Automation (SDA´2003); Dresden, Germany, May, 8 - 9, 2003
  10. Data-Stream-based Computing and Morphware; Joint 33rd Speedup and 19th PARS Workshop (Speedup / PARS 2003), Basel, Switzerland, March 19 - 21, 2003

  11. Trends in Reconfigurable Logic and Reconfigurable Computing; 9th IEEE International Conference on Electronics, Circuits and Systems - ICECS 2002,  September 15-18, 2002, Dubrovnik, Croatia 
  12. (together wirh M. Herz (Agilent Technologies), M. Miranda, E. Brockmeyer (IMEC, Leuven, Belgium), F. Catthoor (IMEC and K.U.Leuven, Belgium):  Memory Organisation for Stream-based Reconfigurable Computing; 9th IEEE International Conference on Electronics, Circuits and Systems - ICECS 2002,  September 15-18, 2002, Dubrovnik, Croatia 
  13. Reconfigurable Computing - Architectures and Methodologies for System-on-Chip; SoC technology seminar "Enabling Technologies for System-on-Chip Development";  Tampere, Finland,  November 19-20, 2001,
  14. Reconfigurable Computing: the Roadmap to a New Business Model - and its Impact on SoC Design; SBCCI 2001 - 15th Symposium on Integrated Circuits  and Systems Design, Brasilia, DF, Brazil, September 10-15, 2001
  15. (invited embedded tutorial) Coarse Grain Reconfigurable Architectures; Asian and South Pacific Design Automation Conference and Exhibit (ASP-DAC 2001), Yokohama, Japan, January 30 - Febr. 2, 2001
  16. Makimoto's Law, the 2nd Design Crisis, and the Future of Reconfigurable Computing; Int'l.   Seminar on Dynamically Reconfigurable Architectures; Schloss Dagstuhl, Germany, June 25-30 2000 -
  17. Reconfigurable Computing; Kongress Highly Reliable Hard- and Software Systems 1999 (HighSys '99), Sindelfingen, Oktober 1999
  18. Freedoms and Necessities in the Knowlege Society;  Freiheiten und Zwaenge in der Wissensgesellschaft ("talk by the fireside")); Annual Symposium of the "Drawing the balance of middle class exonomy politics"  Association for studies of middle class economy (Studiengesellschaft fuer Mittelstandsfragen),  Inzell, Bavaria, Germany. October 1998
  19. On the Application of the KressArray to Rapid Prototyping; Design, Automation and Test in Europe Conference, DATE'98, Paris, France, February 23 - 26, 1998
  20. The Microprocessor is no more General Purpose: why Future Reconfigurable Platforms will win; International Conference on Innovative Systems in Silicon, ISIS'97, Austin, Texas, USA, October 8-10, 1997
  21. A General Approach in System Design Integrating Reconfigurable Accelerators; International Conference on Innovative Systems in Silicon; Austin, Texas, USA, October 9-11, 1996
  22. Xputer: ASIC or Standard Circuit?; Microelectronics Symposium of the German Association for Microelectronics (GME), Oct. 08. - 10, 1993, Dresden, Germany
  23. The Role of Hardware Description Languages in Integrated CAD Systems for VLSI Design (invited paper); CVT Open Workshop; CNET (Centre National d'Etudes de Telecommunication), Meylan (Grenoble), Frankreich, April 1986
  24. Shared Culture: CIF Library, Starting Frames, Scalable Design Rules; NATO Advanced. Study Institute on Design Methodologies for VLSI Circuits, Louvain-la-Neuve, Belgium, 8. - 18. July. 1980
  25. Basics of Structured Design Methodologies: Data Path and Finite State Machines; NATO Advanced. Study Institute on Design Methodologies for VLSI Circuits, Louvain-la-Neuve, Belgium, 8. - 18. July. 1980
  26. On the Interpretive Mechanism of Microprogrammed Systems; EUROMICRO Symposium, Paris, France, 10. - 11. June. 1974

Awards etc.     (last update: 2007)


Invited Presentations in International Company Meetings      (last update: 2007)

  1. Reconfigurable Computing in Medical Image Processing; Siemens AG; Bruchsal, Germany, March 14, 2007
  2. Reconfigurable Computing and its Impact; intel corp Reconfigurable Computing and Communication Workshop, Hillsboro, Oregon, USA, May 15-16, 2003
  3. Reconfigurable Circuits and their Applications; DaimlerChrysler internal FPGA-Workshop; Schwaebisch  Hall; Germany, Sept. 26 - 28, 2000
  4. Reconfigurable Computing: Taking off to Overcome the Microprocessor; parc forum; Xerox Palo Alto Research Center; May 13, 1999
  5. A Framework for Optimization and Programming of application-domain-specific KressArray Architectures; ST microelectronics Corp., Agrate Brianza, Italy, Febr. 17. 1999
  6. The KressArray: a Survey on Progress and Applications; Siemens AG, Corporate Research, Munich, Germany, October 1998
  7. Reconfigurable Computing: From Tinkertoy to Fundamental Computing Paradigm; NEC Laboratories, Princeton, New Jersey, March 1998
  8. (together with Jürgen Becker): Xputers and Their Programming Environment; Invited Tutorial, ARM Advanced RISC Machines, Ltd. Europe, Cambridge, UK, July 24, 1996.
  9. Xputer - Novel High Performance Computers: Principles and Implemenation; IBM Research Laboratories, Boeblingen, Germany June 21, 1990
  10. European Research Projects on CAD for VLSI; JEIDA, Japanese Electrotechnical Industry Association, Keidanren Kaikan, Tokyo, Japan, Sept. 1985
  11. European Research Projects on CAD for VLSI; Fujitsu Corp., Research Labs, Kawasaki, Japan, Sept. 1985
  12. Hardware Description Languages and their Applications; CSELT - Centro Studi et Laboratori Telecommunicazioni, Torino, Italy, Apr.  11  - 12, 1984
  13. Computer Design Languages als Input Sources for LSI CAD, Siemens AG, Central Laboratories, Munich, Germany, Juli 1979

Invited Courses given      (last update: 2004)

  1. Reconfigurable Technologies
    Seminar at Department of Informatics  (Informatics), Kyushu University (Kyushu Univ), Higashi-ku, Fukuoka City, Kyushu, Japan; July 23, 2004,  (part 1 ppt)  (part 2 ppt)

  2. Reconfigurable HPC; Technical University of Talinn (TTU); May 7, 2004, Talinn, Estonia,    (ppt part 1)    (ppt part 2)    (ppt part 3)    (ppt part 4)
  3. Reconfigurable Computing and its Compilation Techniques; Summer School on "Multiprocessor Systems on Chip";  Örebro, Sweden, August 25-27, 2003; jointly organized by the Swedish National Program on Socware, the Strategic Integrated Electronic Systems Research Center at Linköping Universit, and the Competence Center for Circuit Design at Lund University.
  4. Distributed Memory and Datastream-based Reconfigurable Computing; Summer School on "Multiprocessor Systems on Chip";  Örebro, Sweden, August 25-27, 2003; jointly organized by the Swedish National Program on Socware, the Strategic Integrated Electronic Systems Research Center at Linköping Universit, and the Competence Center for Circuit Design at Lund University.

  5. Reconfigurable Computing and its Enabling Technologies -- for the Personal Supercomputer (PS) to replace the PC; THALES internal workshop on Reconfigurable Computing; Orsay, France, Sept 2003
  6. Reconfigurable Computing and its Impact on SoC and beyond; REASON Summer School on FPGA-based and Reconfigurable Systems*, University of Ljubljana, Ljubljana, Slovenia, August 11-15 August 2003.  .---- *) IST-2000-30193
  7. Reconfigurable Computing and its Compilation Techniques; Swedish INTELLECT Summer School on "Multiprocessor Systems on Chip,"  Örebro, Sweden, August 25-27, 2003; jointly organized by the Swedish National Program on Socware, the Strategic Integrated Electronic Systems Research Center at Linköping Universit, and the Competence Center for Circuit Design at Lund University. 

  8. Reconfigurable Computing and its Impact on SoC and beyond; REASON Summer School on FPGA-based and Reconfigurable Systems*, University of Ljubljana, Slovenia, August 11-15, 2003
  9. Reconfigurable Systems; November 13, 14, 21, 2002, CS Department, University of Brasilia, Brasil.
  10. Reconfigurable Computing; internal workshop, CNRS, Paris, July 8 - 12, 2002

  11. Enabling Technologies for Reconfigurable Computing; Post Conference Tutorial (1 full day),  3rd Workshop.on  Enabling Technologies for System-on-Chip Development  (SoC 2001), Tampere, Finland, November 21, 2001
  12. R. Hartenstein (chair), R. Kress, W. Reinig:: Xputers: Principles, Architectures, Performance; Tutorial on Xputers (1 full day); LIRMM, University of Montpellier,  Montpellier, France, Sept. 1995
  13. Introduction to VLSI System Design for Managers;  (2 days) ; CCG (Carl Cranz Gesellschaft), DFVLR (German Aerospace Research Center), Oberpfaffenhofen, Germany, 1989
  14. Introduction to VLSI System Design for Managers;  (2 days) ; CCG (Carl Cranz Gesellschaft), DFVLR (German Aerospace Research Center)    Oberpfaffenhofen, Germany, 1988
  15. Introduction to VLSI System Design;  (5 days) ; CCG (Carl Cranz Gesellschaft), DFVLR (German Aerospace Research Center), Oberpfaffenhofen, Germany, Sept.1988
  16. M Glesner, R. Hartenstein (chair), K. Mueller-Glaser, Th. Vierhaus: Introduction to VLSI System Design; ordered by UNESCO and Portugese Computer Society, Lisbon, Portugal, Aug.1987
  17. Introduction to VLSI System Design for Managers;  (2 days) ; CCG (Carl Cranz Gesellschaft), DFVLR (German Aerospace Research Center),  Oberpfaffenhofen, Germany, 1987
  18. Introduction to VLSI System Design;  (5 days) ; CCG (Carl Cranz Gesellschaft), DFVLR (German Aerospace Research Center), Oberpfaffenhofen, Germany, Sept.1987
  19. Introduction to VLSI System Design for Managers;  (2 days) ; CCG (Carl Cranz Gesellschaft), DFVLR (German Aerospace Research Center), Oberpfaffenhofen, Germany, 1986
  20. Introduction to VLSI System Design;  (5 days) ; CCG (Carl Cranz Gesellschaft), DFVLR (German Aerospace Research Center), Oberpfaffenhofen, Germany, Sept.1986
  21.  Introduction to VLSI System Design;  (5 days), University of Patras, Greece, February 1986  
  22.  Introduction to VLSI System Design; (3 days), Research Center Demokritos, Athens, Greece, February 1986
  23. Introduction to VLSI System Design for Managers;  (2 days) ; CCG (Carl Cranz Gesellschaft), DFVLR (German Aerospace Research Center), Oberpfaffenhofen, Germany,  1985
  24. Introduction to VLSI System Design;  (5 days) ; CCG (Carl Cranz Gesellschaft), DFVLR (German Aerospace Research Center)    Oberpfaffenhofen, Germany, Sept. 1985
  25. Introduction to VLSI System Design for Managers;  (2 days) ; CCG (Carl Cranz Gesellschaft), DFVLR (German Aerospace Research Center)    Oberpfaffenhofen, Germany,  1984
  26. Introduction to VLSI System Design;  (5 days) ; CCG (Carl Cranz Gesellschaft), DFVLR (German Aerospace Research Center), Oberpfaffenhofen, Bavaria, Germany, April 1984 
  27. Introduction to VLSI System Design for Managers;  (2 days) ; CCG (Carl Cranz Gesellschaft), DFVLR (German Aerospace Research Center)   Oberpfaffenhofen, Germany,  1983
  28. Introduction to VLSI System Design;  (5 days) ; CCG (Carl Cranz Gesellschaft), DFVLR (German Aerospace Research Center)  Oberpfaffenhofen, Bavaria, Germany, April 1983, -
  29. Introduction to VLSI System Design; (3 days), Elektrotechniek department, Techn. Hochschule, Twente, Enschede, Netherlands, Nov. 17. - 19,. 1982
  30.  Introduction to VLSI System Design; (3 days) GMD (Gesellschaft fuer Mathematik und Datenverarbeitung) Schloss Birlinghoven, St. Augustin, Germany, Oct. 18. - 20, 1982
  31. Introduction to VLSI System Design, (3 days), GMD (Gesellschaft fuer Mathematik und Datenverarbeitung),  Schloss Birlinghoven, St. Augustin, Germany, Sept. 27. - 29, 1982
  32.  Introduction to VLSI System Design;  (3 days), INPG Grenoble, France, Oct. 1982

  33. Introduction to VLSI System Design; (3 days), Siemens- AG, Zentrallabor, Munich-Neuperlach, Germany,  (June 1982)
  34.  Introduction to VLSI System Design;   (3 days), Siemens-AG, Geraetewerk Karlsruhe (4. / 7. / 9. June 1982)
  35. Hardware Description Languages and their Applications; CSELT - Centro Studi et Laboratori Telecommunicazioni, Torino, Italy,  (27. Feb. - 2. March. 1983)
  36. (part of a 3 week VLSI design course); Hardware Description Languages and their Applications;  Schuola Guglielmo Reiss-Romoli, L'Aquila, Italy, 1982


Other Invited Presentations       (last update: 2003)

  1. Datastream-based Reconfigurable Computing;  Dresdner Arbeitstagung Schaltungs- und Systementwurf (DASS´2003), in conjunction with  Workshop System Design Automation (SDA´2003); Dresden, Germany, May, 8 - 9, 2003
  2. Data-stream-based Computing, Enabling Technology for Reconfigurable Computing; November 22, 2002, Seminar, EE department (ENE), University of Brasilia, Brasil,
  3. Data-stream-based Computing, Enabling Technology for Reconfigurable Computing; November 22, 2002, Seminar, EE department (ENE), University of Brasilia, Brasil.
  4. Stream-based Arrays: Converging Design Flows for both, Reconfigurable and Hardwired; IFIP International Conference on Very Large Scale Integration ( VLSI-SoC 2001 ), December 2- 4, 2001,  Montpellier, France
  5. Chances of the IT Industry; Heinz Nixdorf Forum Future and Professsion (Zukunft und Beruf), Paderborn, Germany, 6. - 10. March 2001;
  6. Programming Reconfigurable Circuits: just Logic Synthesis on a Strange Niche Platform? Scientific Colloquium of the Computer Science Department, Technical University of Dresden, Germany, 8. Juni  2000
  7. Will Reconfigurable Computing overcome the microprocessor?;  Annual Symoiosium INFOfest'98, Budva, Montenegro, Yugoslavia, September 26 - October 3, 1998
  8. Another Point of View on the Internet; INFOfest'98, Budva, Montenegro, September 26 - October 3, 1998
  9. Systems for Electronic Business on the Internet; Invited talk, Annual Symposium INFOfest'98, Budva, Montenegro, Yugoslavia, September 26 - October 3, 1998
  10. From  FPGA to "Reconfigurable Computing; Computer Science Colloquium, Universiy of Koblenz, Germany, July 1998
  11. Reconfigurable Computing with KressArray and Xputer; Astronomisches Recheninstitut (ARI), University of Heidelberg, Heidelberg, Germany, July 1998
  12. From FPGA to "Reconfigurable Computing; Informatik-Kolloquium, University of  Karlsruhe, Germany, June 1998
  13. Reconfigurable Computing with KressArray and Xputer machine paradigm; University of Belgrade, Yugoslavia, May 1998
  14. Reconfigurable Computing with KressArray and Xputer machine paradigm, Colloquium, Carnegie Mellon University, Pittsburgh, PA, March 1998
  15. Reconfigurable Computing: From Tinkertoy to Fundamental Computing Paradigm; University of California, Irvine, January 1998
  16. Reconfigurable Computing: From Tinkertoy to Fundamental Computing Paradigm; San Jose State University, January 1998
  17. Reconfigurable Computing: From Tinkertoy to Fundamental Computing Paradigm; University of Southern California, Los Angeles, January 1998
  18. Trends ini reconfiguriable circuits; Colloquium, TU-Darmstadt, Germany, Dec. 8, 1997.
  19. Why a Second Machine paradigm?; Colloquium, TU Darmstadt, Germany Dec. 8, 1997.
  20. Reconfigurable Computing: an Alternative to ASICs?; Colloquium TU Chemnitz, Germany, Nov. 26, 1997.
  21. Reconfigurable Computing: an Alternative to ASICs?; Colloquium, University of Linz, Austria, Nov. 20, 1997.
  22. Reconfigurable Computing:  an Alternative to ASICs?; Colloquium, University of Erlangen, Germany, July 18, 1997.
  23. A Machine Paradigm for dynamically reconfigurable Processors; Colloquium, University of Jena, Mai 28, 1997.
  24. Computer Engineering: fifth wheel of the wagon?; 60th Birthday Colloquium, University of Passau, Germany, Mai 5, 1997.
  25. Reconfigurable Hardware: form Tinker Toy to fundamental Computing Paradigm; Colloquium, IMEC Leuven, Belgium, April 18, 1997.
  26. High-Performance Computing: about Scenes and Crises; GI/ITG Workshop on Custom Computing, Schloss Dagstuhl, Germany, June 1996
  27. Teach our Schools the wrong Subjects?; Wissenschaftspressekonferenz, Bonn-Bad Godesberg, Germany, Dez. 1995
  28. Quo vadis Computer Science?; Colloquium, University of Rostock, Germany, Okt. 1995
  29. Xputers: Principles, Architectures, Performance; Tutorial on Xputers: New Horizons in Computing Power, University of Montpellier, France, Sept. 1995
  30. Xputers, a New Computational Paradigm;  Institute of Microelectronics; Singapore, Nov. 1994
  31. Xputers, a New Computational Paradigm;  Colloquium, School of Computing, Curtin University of Technology, Perth, Australia, Nov. 1994
  32. Xputers, a New Computational Paradigm; Kolloquiumsvortrag, University of Augsburg, Febr..02, 1993, Augsburg, Germany,
  33. A new Machine Paradigm as an Alternative to von Neumann: a consequence of FPLD-/FPGA Application; IMS, Fraunhofer Institute of Microelectronic Systems, Duisburg, March 1992
  34. Xputers: A Novel High-performance Machine Paradigm; Colloquium, University of Catania, Italy, April 1992
  35. Xputers: A Novel High-performance Machine Paradigm; Colloquium, University of Linkoeping, Sweden, May 1992
  36. Xputer: ein neues Hochleistungs-Maschinenparadigma; Fa. Hermstedt, Mannheim, Germany, Oktober 1992
  37. Xputer: a Machine Paradigm for better efficiency of Hardware; Colloquium, Fern-Universitaet Hagen, Germany, Feb. 1991
  38. Xputer: a Machine Paradigm for better efficiency of Hardware; Colloquium, FAW, University of Ulm, Germany, April 1991
  39. Xputer: a Machine Paradigm for High Performance Computers;  Colloquium, GMD, Schloss Birlinghoven, St. Augustin, Germany, April 1991
  40. Xputers as High Performance Computers: their Principles and Implementations; ITT Corporation, Freiburg, Germany, May 1991
  41. A High Performance Machine Paradigm Based on Auto-Sequencing Data Memory; Information Science Inastitute (ISI), University of Southern California, Los Angeles, Sept. 1991
  42. A High Performance Machine Paradigm Based on Auto-Sequencing Data Memory;  ICSI International Computer Science Institute, Berkeley, Sept. 1991
  43. A High Performance Machine Paradigm Based on Auto-Sequencing Data Memory;  George Washington University, Washington, DC, Okt. 1991
  44. A Novel ASIC Design Approach Based on a New Machine Paradigm; Colloquium, University of Tainan, Taiwan, Sept. 1991
  45. A Flexible Hardware Accelerator and its Applications in EDA, 16th CAVE Workshop, Gent, Belgien, Dezember 1990
  46. Xputer: a Machine Paradigm for better efficiency of Hardware; Fern-Universitaet Hagen, 15. November 1990
  47. Xputer: a Machine Paradigm for better efficiency of Hardware; City Polytechnic of Hong Kong, Hong-Kong, Oct 16, 1990
  48. Xputer: a Machine Paradigm for better efficiency of Hardware; University of Hong Kong, Hong-Kong, Oct 15, 1990
  49. Xputer: a Machine Paradigm for better efficiency of Hardware, Waseda University, Tokyo, Japan, Oct 12, 1990
  50. Xputer - Novel High Performance Computers: Principles and Implemenation; Electrotechnical Laboratory at Ibaraki, Kawasaki, Japan, Oct 11, 1990
  51. Implementation of Parallel Algorithms on Xputer: More Performance from Less Hardware, Colloquium, University of Kyoto, Kyoto, Japan, Oct. 8, 1990
  52. Xputer: a new Machine Paradigm for Very High Performance Computers; Lessacher Informatik-Koilloquien, Lessach, Austria, Sep 18 - 21, 1990
  53. Xputer: a new Machine Paradigm for Very High Performance Computers; University of Mannheim, June 12, 1990
  54. Xputer: a Machine Paradigm for improved efficienca of Hardware, Colloquium, University of Karlsruhe, June 11, 1990
  55. Xputers: Innovative High Performance Computers - their Principles and Implementation; Techn. University of Vienna, Austria, May 4, 1990
  56. Xputers: Innovative High Performance Computers - their Principles and Implementation;  Universidad Politecnica Catalunya, Barçelona, Spain, Febr. 26, 1990
  57. Xputers: Innovative High Performance Computers - their Principles and Implementation;  Universidad Politecnica de Madrid, Spanien, Februar 23, 1990
  58. Xputers: Innovative High Performance Computers - their Principles and Implementation;  Universidad Complutense, Madrid, Spain, Febr. 22, 1990
  59. Xputer: A Universal Accelerator for Digital Signal Processing, I+D Telefónica y Desarollo, Madrid, Spain, Febr 21, 1990
  60. Xputer: A Novel Machine Paradigm for efficient Implementation of parallel Algorithms, Colloquium, Universidad Cantabria, Santander, Spain, Febr 20, 1990
  61. Xputers: Innovative High Performance Computers - their Principles and Implementation; Colloquium, University of Tuebingen, Germany, Febr. 6, 1990
  62. DesignTools at Higher Abstraction Levels;  Professor Conference "Mikroelektronik" of the Federal Ministry of Post and Telecommunication; Darmstadt, Germany, Nov. 1987
  63. KARL-related VLSI CAE Tools; PUC (Catholic University), Rio de Janeiro, Brasil, Nov. 1987
  64. Research on VLSI Design at Kaiserslautern University; UFRJ (Bundes-Universitaet), Rio de Janeiro, Brasil, Nov. 1987
  65. RT Level CAE Tools for VLSI Design; IBM Centro Scientifico; Rio de Janeiro, Brasil, Nov. 1987
  66. Introduction to using KARL in VLSI Design; CTI (Centro Technologica para Informatica) Campinas, SP, Brazil, Oct. 1987
  67. VLSI CAE Tool Integration to support Design for Testability at Early Phases of the Design Process; CTI (Centro Technologica para Informatica) Campinas, SP, Brasil, Oct. 1987
  68. The E.I.S. Project - a German Multi University Effort of Research and Instruction in VLSI Design; CTI (Centro Technologica para Informatica) Campinal, SP, Brasil, Oct. 1987
  69. VLSI Structural Modelling by RT Language Expressions; CTI (Centro Technologica para Informatica) Campinas, SP, Brasil, Oct. 1987
  70. Introduction to Using KARL for VLSI Design; Computer Science Department, UFRGS (Bundes-Universitaet Rio Grande do Sul), Porto Allegre, RGS, Brasil, Oct. 1987
  71. MoM - a semi von-Neumann Accelerator Architecture; Computer Science Department, UFRGS (Bundes-Universitaet Rio Grande do Sul), Porto Allegre, RGS, Brasil, Oct. 1987
  72. The E.I.S. Project and future aspects of Research and Instruction in VLSI Design in the Federal Republic of Germany; Jahrestagung der Brasilianischen Gesellschaft fuer Mikroelektronik, Porto Allegre, RGS, Brasil, Oct. 1987
  73. The E.I.S. Project - a Nation-wide Effort of Research and Instruction in VLSI Design in the Federal Republic of Germany; CTI (Centro Technologica para Informatica) Campinas, SP, Brasil, Oct. 1987
  74. MoM - a semi von-Neumann Accelerator Architecture; CTI (Centro Technologica para Informatica) Campinas, SP, Brasil, Oct. 1987
  75. The E.I.S. Project - a Multi University Effort of Research and Instruction in VLSI Design in the Federal Republic of Germany; ITA (Inst. Technologica para Aeronautica), CTA (Centro Technologica para Aeronautica), Sao Jose dos Campos, SP, Brasil, Oct. 1987
  76. Research on VLSI Design Methodologies at Kaiserslautern University, ITA (Inst. Technologica para Aeronautica), CTA (Centro Technologica para Aeronautica), Sao Jose dos Campos, SP, Brasil, Oct. 1987
  77. Structured VLSI Design using Structural Modelling by RT Language Expressions; Dept. of Electrical Engineering, UNICAMP (Universitaet) Campinas, SP, Brasil, Oct. 1987
  78. Synergistic VLSI CAE Tool Integration at Early Phases of the Design Process; Computer Science Dept., UNICAMP (Universitaet) Campinas, SP, Brasil, Oct. 1987
  79. Integration of Conceptual VLSI Design and Test Development; CPqD TELEBRAS (Brasilian Federal Research and Development Center for Telecommunication), Campinas, SP, Brasil, Oct. 1987
  80. The German Multi University E.I.S. Project; CPqD TELEBRAS (Brasilian Federal Research and Development Center for Telecommunication), Campinas, SP, Brasil, Oct. 1987
  81. MOM - Map-oriented Machine: A Flexible Architecture for Image Processing, EUROMICRO Symposium; Portsmouth, UK, Sept. 1987
  82. Recent Developments in CAD for VLSI;  Elektrotechnical Colloquium; University of Duisburg, Germany, Oct. 1985
  83. Recent Developments in CAD for VLSI; INPG (Institute Nationonal Polytechnique de Grenoble), Grenoble, France, Feb 23. - 24, 1984)
  84. Impact and Education of the 'New Microelectronics; Colloquium, Fern-University of Hagen, Dec. 21, 1983
  85. Impact and Education of the 'New Microelectronics; Colloquium, Technical University, Vienna, Austria, 6. 12. 1982
  86. The 'New Microelektronics': new forms of cooperation between Informatics and Semiconductor Technology;  Colloquium, University of Erlangen-Nuremberg, Germany, Nov. 14, 1982
  87. The 'New Microelectronics': new forms of cooperation between Informatics and Semiconductor Technology;  Annual Conference of the German Computer Society (GI - Gesellschaft fuer Informatik), University of Kaiserslautern,. Oct. 5 - 7, 1982
  88. The 'New Microelektronics': new forms of cooperation between Informatics and Semiconductor Technology; Colloquium, Techn. University of Munich, Germany, July 22,. 1982
  89. The 'New Microelektronics': new forms of cooperation between Informatics and Semiconductor Technology; Colloquium, University of Brauschweig, June 14, 1982
  90. The 'New Microelektronics': new forms of cooperation between Informatics and Semiconductor Technology; Colloquium, Univ.of Erlangen, May  5. 1982
  91. The 'New Mcroelektronics': new forms of cooperation between Informatics and Semiconductor Technology;  (invited presentation to the board of directors)  GMD Research Center, Schloss Birlinghoven, May 10, 1982
  92. Hardware Description Languages and their Applications;  Colloquium, Linkoepings University, Linkoeping, Sweden, 1980
  93. Hardware Description Languages and their Applications;  Colloquium, University of Karlsruhe, Karlsruhe, Germany,  Nov. 1979
  94. Trends in CAD for VLSI ; Seminar*, Department of Informatics, University of  Kaiserslautern, 1979
  95. Optimized Lab Course Equipment for Introducing LSI Components ;  Seminar*,  Department of Informatics, University of Kaiserslautern , 1979
  96. Hardware Description Languages ; Informatics Colloquium*, University of Kaiserslautern, 1975
  97. On the Use of  KARL for Description and Design of Hardware for MSI or LSI Chips;  Colloquium of the Computer Science Department, University of Maryland, College Park, Maryland, 13. Sept. 1974
  98. Hardware Description Languages and their Applications; Colloquium, University of Maryland, College Park, Maryland, Sept. 13, 1974
  99. Concepts of Mikroprogramming; Conference on  Minicomputers and Peripherals; Frankfurt, Germany., Feb. 15, 1973
  100. Concepts of Mikroprogramming; Techn. University of Vienna, Austria, Nov. 19, 1973
  101. Concepts of Mikroprogramming; Techn. University of Graz, Austria, Nov. 20, 1973
  102. Concepts of Mikroprogramming; Austrian Cybernetics Association, Vienna, Austria, Nov. 22, 1973
  103. Hierarchy of Interpreters for Modelling Complex Digital Systems; Colloquium, Techn, University of  Darmstadt, Germany, Feb. 13, 1973
  104. Hiierarchy of Interpreters for Modelling Complex Digital Systems; Colloquium, University of Aarhus, Denmark, May 17, 1973
  105. Hierarchy of Interpreters for Modelling Complex Digital Systems; Colloquium, University of Hamburg, May 21, 1973
  106. How to Teach Computer Organization ; Colloquium*, University of Bonn , Germany, 29. Jan. 1973
  107. How to Teach Computer Organization Seminar* Institute for Informatics IV, University of Karlsruhe , Germany, 5. Feb. 1973
  108. An Example Computer Architecture for Dynamic Microprogramming ; Seminar fuer Mikroprogrammierung, Inst. f. Informatik, University of Karlsruhe , Germany, 8. Feb. 1972
  109. A Flexible Breadboard System for Experiments in Undergraduate Computer Hardware Lab Courses ; 2nd Annual Conference of the GI (Gesellschaft fuer Informatik), Karlsruhe , Germany, 4. Oct. 1972
  110. CRT I/O Devices and their Applications in Man / Machine Dialogue; Conference*, Elektrotechnischer Verein Mittelbaden (subdivision of VDE), Karlsruhe , Germany, Jan. 12,. 1971
  111. Logic Analyzers ; Seminar*, Institute for Information Processing, University of Karlsruhe , Germany, May 23, 1971
  112. On the Hardware / Software Interface ;  Informatics Colloquium*, University of Karlsruhe , Germany, May 19,  1971
  113. Microoperations and their Hardware Implementation ; Seminar* on Microprogramming, Inst. f. Informatik, University of Karlsruhe , Germany, 14. Dec. 1971
  114. Designing Finite State Machines for Character Recognition from Regular Expressions ;  Seminar*, Institute for Information Processing, University of Karlsruhe , Germany, Jan 17, 1969
  115. CRT Screen I/O and its Applications ; Informatics Colloquium*, University of Karlsruhe , Germany, July 14, 1969
  116. CRT I/O Devices and their Applications ;  Seminar*, Institute for Information Processing, University of Karlsruhe , Germany, May 3, 1968.
  117. About F.S.M. Controller Simulation ;  Seminar*, Institute for Information Processing, University of Karlsruhe , Germany, July 28, 1967
  118. Automatic Synthesis and Minimization of  State Transition Tables for Automatic Character Recognition ;  Seminar, Institute for Information Processing, University of Karlsruhe , Germany, 27. 10. 1967
  119. Serial Processing Methods in Character Recognition ; Seminar*, Institute for Information Processing, University of Karlsruhe, Nov 11,. 1966
  120. Formal methods in F.S.M. Controller Analysis and Synthesi ; Seminar*, Labor fuer Elektronics Laboratory, Nucleear Research Center, Karlsruhe, Germany, June 1965
  121. Optical Methods in Pattern Recongnition ;  Seminar*, Institute for Information Processing, University of Karlsruhe , Germany, 2. July 1965
  122. About Display Techniques for Computer I/O. ;  Seminar*, Institute for Information Processing, University of Karlsruhe , Germany, 17. Dec. 1965

Contributions as a panelist       (last update: 2002)

  1. Panel on Embedded Architectures: Configurable, Re-configurable, or what?  together with: Pierre Paulin, STMicro (moderator), Henk Corporaal, IMEC, Oz Levia, Improv Systems,  Marco Pavesi, Italtel, Chris Rowen, Tensilica. - CASES 2002 (International Conference on Compilers, Architecture, and Syntheses for Embedded Systems), October 8-11, 2002, Grenoble, France, co-located with EMSOFT 2002 (Oct 7-9) 
  2. Panel "Reconfigurable Computing"; together with Lech Józwiak (chair), Steve Guccione (Xilinx), Rolf Ernst (TU Braunschweig), Kjell Torkelsson (Ericsson), Adam Postula (U Queensland): DSD'2001 - EUROMICRO SYMPOSIUM ON DIGITAL SYSTEM DESIGN:  Architectures, Methods, and Tools, Warsaw, Poland, September 4 - 6, 2001.
  3. Panel* "today at highschool - tomorrow a boss";  together with : Juergen Mayer, TV station WDR 2 (moderator); Marco Elling, CEO BloxAG,  Muenster; Prof. Dr. Stefan Fischer, International University in Germany, Bruchsal; Matthias Kenter, Institut der Deutschen Wirtschaft, Cologne; Dr. Ruediger Schiller, Deutsche Ausgleichsbank, Bonn    --- Heinz Nixdorf Forum Zukunft und Beruf, Paderborn, Germany, March 6 - 10, 2001;
  4. Panel* "Freedoms and Necessities in the Knowlege Society" ("talk by the fireside"); Symposium on "Drawing the balance of middle class exonomy politics", Annual Symposium of the Association for studies of middle class economy (Studiengesellschaft fuer Mittelstandsfragen), Inzell, Bavaria, Germany. Oct. 1998
  5. Panel* "Information Society and Education"; togehter with Prof.  Dr. M. Polke  (moderator), and others, Conference on Achitecture of Computing Systems (ARCS'97), Rostock, Germany, Sept 8-11, 1997 
  6. Panel "Is Germany hostile to innovations?"  together with Dr. jur. Manfred Genz, DaimlerChrysler (organizer), Leitung: Prof. Dr. Helmut Baumgarten , TU Berlin (moderator), and others ... 4th IMT annual conference on "Management and Technology in Global Competition", Berlin, Germany, Nov. 6 - 7, 1966  Hilton Hotel am Gendarmenmarkt
  7. Panel* "Is Germany hostile to innovations?", together with Prof. Dr. Klaus Brockhoff, Univ
    érsity of Kiel (moderator); Marco Boerries, founder Star Division Software Berlin/Fremont; Wolfgang Branoner, Minister, Senate of Berlin; Paulus Neef, founder PIXELPARK Multimedia GmbH Berlin, concluded by* Dr. h.c. Lothar Spaeth, CEO Jenoptic, Jena, Germany: "Chances and Problems with Innovations in Germany"; .4th IMT annual conference on "Management and Technology in Global Competition", Berlin, Germany, Nov. 6 - 7, 1996

  8. panel "Why can't we agree on a Single Standard?", (organized by Tamio Hoshino, NTT LSI Laoratories, Japan) together with Daniel D. Gajski, UC Irvine, Osamu Karatsu, NTT Corp., Tokyo, Japan, Erich Marschner, CLSI, Rockville, MD, USA, Nick Peeling, Ministry of Defense, Malvern, UK, Robert Piloty, TU Darmstadt, Germany; ACM / IEEE Design Automation Conference 1989 (DAC '89), Las Vegas, Nevada, USA June 1989
  9. panel "Why VLSI Specification?", together with: Jonathan Allen, M.I.T, Cambridge, USA, Dwight Hill, IT&T Bell Labs, Murray Hill, NJ, USA, Carlo Sequin, UC Berkeley, Nick Tredennick, IBM Yorktown Heights, Niklaus Wirth, ETH Zuerich; IFIP Summer School on VLSI Design; Beatenberg, Switzerland, 1986

Refereed Documented Presentations       (last update: 2004)

  1. (together with: R. Jacobi, M. Ayala Rincon, L. Carvalho, C. Llanos): Reconfigurable Systems for Sequence Alignment and for General Dynamic Programming; 3rd Brasilian Workshop on  Bioinformatics (wob 2004), Brasília, Distrito Federal, Brazil, October 20-22, 2004

  2. (in preparation) (together with:  M. Ayala-Rincón, R. P. Jacobi and C. Llanos, Designing Arithmetic Digital Circuits via Rewriting-Logic, (Postscript), 2004
  3. (together with: C. LLanos, R. P. Jacobi, M. Ayala-Rincón): A Dynamically Reconfigurable System for Space-Efficient Computation of the FFT, (ps, pdf). To appear in Soc. Mex. Comp. Proc. International Conference on Reconfigurable Computing and FPGAs 2004 (ReConFig'04), Colima, Mexico, Sept 20-21, 2004
  4. (submitted) (together with: M. Ayala-Rincón, C. Llanos, R. P. Jacobi): Prototyping Time and Space Efficient Computations of Algebraic Operations over Dynamically Reconfigurable Systems Modeled by Rewriting-Logic, (pdf), submitted 2004.
  5. (together with:  M. Ayala-Rincón, R. B. Nogueira, R.P. Jacobi, C. H. Llanos): Modeling and Prototyping Dynamically Reconfigurable Systems for Efficient Computation of Dynamic Programming Methods; ACM Proc. 17th Symposium on Integrated Circuits and System Design -CHIP ON THE REEFS - SBCCI'04, Porto de Galinhas, Pernambuco, Brazil, September 7-11, 2004,  (postscript,  Pdf)
  6. (together with M. Ayala-Rincón, R. B. Nogueira, R. P. Jacobi, and C. Llanos): Modeling a Reconfigurable System for Computing the FFT in Place via Rewriting-Logic, (postscritp, X MB; PdfPDF, X MB). To appear in IEEE CS Press Proc. 16th Symposium on Integrated Circuits and System Design - SBCCI 03, Sã/o Paulo, Brasil, (Sep 8-11, 2003).
  7. (together with  R. P. Jacobi, M. Ayala-Rincón and C. Llanos): Using Rewriting-Logic Notation for Funcional Verification in Data-Stream Based Reconfigurable Computing, (postscritp, X MB; Pdf, X MB). To appear in Forum on Specification and Design Languages - FDL 03, Frankfurt, Germany, (Sep 23-26, 2003).
  8. (together with M. Ayala-Rincón, R. Maya Neto, R. P. Jacobi, and C. Llanos): Architectural Specification, Exploration and Simulation Through Rewriting-Logic, (Postscript, 134 KB). In Colombian Journal of Computation, Vol 3(2):15 pages, 2003.
  9. (embedded tutorial) A Decade of Reconfigurable Computing - a Visionary Retrospective; Int'l Conf. and Exhibit on Design, Automation and Test in Europe (DATE 2001); Munich, Germany, March 13 - 16, 2001
  10.  Interfacing the MoM-PDA to an Internet-based Development System; 32th Annual Hawaii Int'l Conf. on System Science (HICSS-32), Hawaii, USA, January 5 - 8,1999
  11. A Revival of Systolic Arrays by Course Granularity Reconfigurable Circuits, Seminar on Dynamically Reconfigurable Architectures, Schloss Dagstuhl, Germany, February 22 - 27, 1998
  12. Parallelization in Co-Compilation for Configurable Accelerators; Asia and South Pacific Design Automation Conference, ASP-DAC-98, Yokohama, Japan, Feb. 10-13, 1998
  13. An Innovative Platform for Embedded System Design ; Workshop Zielarchitekturen Eingebetteter Systeme, ZES'97, in conjunction with the Fachtagung Architekturen von Rechensystemen ARCS'97, Rostock, Germany, September 11, 1997
  14. An Embedded Accelerator for Real World Computing; IFIP International Conference on Very Large Scale Integration, VLSI'97, Gramado, Brazil, August 26-29, 1997
  15. A Two-level Co-Design Framework for data-driven Xputer-based Accelerators; 30th Annual Hawaii Int. Conf. on System Science (HICSS-30), January 7-10, Wailea, Maui, Hawaii, USA, 1997.
  16. Co-Design and High Performance Computing: Scenes and Crisis; Reconfigurable Technology for Rapid Product Development & Computing, Part of SPIE International Symposium '96, Boston, USA, Nov. 1996
  17. A Synthesis System for Bus-based Wavefront Array Architectures; ASAP 96 Application Specific Array Processors, Chicago, USA, August 1996
  18. Two-Level Hardware/Software Partitioning Using CoDe-X; Int. IEEE Symp. on Engineering of Computer Based Systems (ECBS), Friedrichshafen, Germany, March 1996
  19. Two-Level Partitioning of Image Processing Algorithms for the Parallel Map-oriented Machine; 4th Int'l Workshop on Hardware/Software Co-Design CODES/CASHE '96, Pittsburgh, USA, March 1996
  20. CoDe-X: A Novel Two-Level Hardware/Software Co-Design Framework; VLSI Design 96 Conf., Bangalore, India, January 1996
  21. CoDe-X: A Novel Two-Level Hardware/Software Co-Design Framework; 9th International Conference on VLSI Design, Bangalore, India, Jan. 1996
  22. A Reconfigurable Parallel Architecture to Accelerate Scientific Computation; International Conference on High Performance Computing, New Delhi, India, Dec. 1995
  23. Data-procedural Languages for FPL-based Machines; 4th Int'l  Workshop On Field Programmable Logic And Applications, FPL-94, Prague, September 7-10, 1994
  24. Parallelizing Compilation for a Novel Data-Parallel Architecture; PCAT-94, Parallel Computing: Technology and Practice, Wollongong, Australia, Nov. 1994
  25. KARL and ABL; (Invited Paper), NATO Advanced Study Institute on Fundamentals and Standards in Hardware Description Languages, 16. - 26.04.93, Il Ciocco, Barga, Italy, 1993
  26. CASHE, Using a New Machine Paradigm; Workshop Codes/CASHE´93, 24. - 27.05.93, Igls, Innsbruck, Austria, 1993
  27. Hardware/Software Co-Design; 3rd International Workshop on Field Programmable Logic and Applications, 07. - 10.09.93, Oxford, England, 1993
  28. MoPL-3: A New High Level Xputer Programming Language; 3rd International Workshop on Field Programmable Logic and Applications, 07. - 10.09.93, Oxford, England, 1993
  29. A Novel High-performance Machine Paradigm and ASIC Design Methodology; International Design Automation Workshop ("Russian Workshop"), 29. - 30. 06. 92, Moskau, Russia, 1992
  30. Novel High Performance Machine Paradigms and Fast-Turnaround ASIC Design Methods: a Consequence of, and a Challenge to, Field-programmable Logic ; 2nd International Workshop on Field-Programmable Logic and Applications, 31. 08. - 02. 09. 92, Vienna University of Technology, Vienna, Austria, 1992
  31. A High Performance Machine Paradigm Based on Auto-Sequencing Data Memory; HICSS-24 Hawaii International Conference on System Sciences, Koloa Hawaii, January 1991
  32. Xputer: Neuartige Hochleistungsprozessoren, deren Prinzipien und Realisierungen; University of Stuttgart,  Germany, Jan. 1991
  33. Xputer use for Acceleration of Neuronal Network Simulation; 3rd Int. Workshop on Adaptive Learning and Neuronal Networks, Schloss Reisensburg, Germany, 2.-7.7 1991
  34. A Technology Adaptable Device Generator as a Frontend for Layout Generators, EDAC '90 - European Design Automation Conference, Glasgow, UK, March 1990
  35. Xputers - An Open Family of Non von Neumann Architectures, ITG/GI-Konferenenz ueber die Architektur von Rechensystemen, Munich, March 5 - 7, 1990
  36. Using Xputers as Inexpensive Universal Accelerators in Digital Signal Processing; Bilkent '90 International Conference on New Trends in Communication, Control and Signal Processing, Ankara, Turkei, Juli 1990
  37. The Machine Paradigm of Xputers and its Application to Digital Signal Processing Acceleration, International Conference on Parallel Processing, St. Charles, Illinois, August 1990
  38. A Novel Paradigm of Parallel Computation and its Use to Implement Simple High Performance Hardware; Internationale Konferenzen CONPAR '90 und VAPP IV, Zurich, Schweiz, September 1990
  39. Extremely Efficient Array Emulation by a Computational Device using Innovative Machine Principles; ASICS Open Workshop on Regular Array Architectures, Patras, Greece, 24. September 1990
  40. A Novel Paradigm of Parallel Computation and its Use to Implement Simple High Performance Hardware, InfoJapan '90, Tokio, Japan, October 1990
  41. Mapping Systolic Arrays onto the Map-Oriented Machine (MoM); International Workshop on Systolic Arrays, Killarney, Mai 1989
  42. SYS3 - A CHDL-Based Systolic Synthesis System; IFIP Int'l Symposium on Hardware #descriptive Languages 1989 (CHDL '89), Washington, D.C. June 1989
  43. A Pseudo Parallel Architecture for Systolic Algorithms; IFIP Workshop on Parallel Architectures in Silicon, Grenoble, December 1989
  44. Some new features in KARL-4 and superKARL - a survey; 2nd ABAKUS Workshop, Innsbruck, Austria, 4. - 7.9.1988
  45. Integration of Simulation, Test Development and Test in a High Level Design Environment; IFIP TC10 Working Conference on VLSI Architecture, Pisa, Italien, 20. - 22.09.1988
  46. Computer Structure Partitioning Schemes; IFIP TC10 Working Conference on VLSI Architecture, Pisa, Italy, 20. - 22.09.1988
  47. Design for Testability by Integration of Functional Simulation and Test Pattern Development; NTG workshop (Nachrichtentechnische Gesellschaft, Stuttgart, 1986
  48. Future Work on KARL and related CAD Tools; ABAKUS Workshop, Passau, Germany, June 1986
  49. ABLED - ein CAD Tool for Designingn Digital Systems*, Proc. DECUS Muenchen Symposium, Stuttgart, Germany, 1986
  50. Higher Level Simulation and CHDLs; IFIP Summer School on VLSI Design; Beatenberg, Switzerland, 1986
  51. CAD Tools for Experimenting with Alternative VLSI Architectures; IFIP Workshop on VLSI Architectural Design; Torino, Italy, 1986
  52. Map-Oriented Processing: Accelerator concept and VLSI design environment for a class of data processing problems; Seminar*, IMS, Fraunhofer-Institute for Microelectronic Systems, Duisburg, Germany, July 1986
  53. Towards Engineering System Sciences; Annual Symposium of SEFI (Societé Européenne de Formation des Ingenieurs), Madrid, Spane, Sept. 1985
  54. Towards Engineering System Sciences.,   GI Conference on Modeling digital Systems, Bernried, Starnberger See, Germany, June 24. - 25, 1982
  55. Towards the personal CAD station; Mikroelektronics Congress, Munich, Germany, Nov. 1982
  56. KARL as an interpretive graphic input to VLSI CAD tools; 2nd Int'l. Symposium on Computer Hardware Descriptions Languages and their Applications (CHDL), Palo Alto, Oct. 1979
  57. A Computer for the Hardware Description Language KARL; Annual Conference of the GI (Gesellschaft fuer Informatik), Berlin, Sept. 1978 
  58. Generalized Principles of Microprogrammable Computer Structures*; Annual Conference of the GI (Gesellschaft fuer Informatik), Berlin, Sept. 1978 
  59. Hierarchy of Interpreters for Modelling Complex Digital Systems; Colloquium,  Annual Conference of the GI (Gesellschaft fuer Informatik), Hamburg, Oct. 8 - 10, 1973
  60. On the Use of  KARL for Description and Design of Hardware for MSI or LSI Chips; 2nd Int'l. Symposium on Computer Hardware Descriptions Languages and their Applications (CHDL), Darmstadt, Germany, July 31. - Aug 1, 1974
  61. The Use of ABL for Design and Description of Hardware Structures; IFIP 2nd Int'l. Symposium on Computer Hardware Descriptions Languages and their Applications (CHDL), Darmstadt, Germany, 31. July. - 1. Aug. 1974
  62. Microprogramming Concepts - A Step towards Structured Hardware Design; 7th ann. Symposium on Mircoprogramming (MICRO'74), Palo Alto, 29. Sept. - 2. Oct. 1974
  63. Concepts of Microprogramming ;   GI-NTG-Conference 'Structure and Operation of Computers', Braunschweig , Germany, 20. - 22. March. 1974
  64. Increased Hardware Complexity  -  A Challenge to Computer Science Education; 1st Int'l. Symposium for Computer Architecture (ISCA), Gainesville, Florida, Dec. 9. - 11, 1973
  65. A special Machine System for Visual Pattern Recognition (H. Kazmierczak, F. Holdermann, speaker: R. Hartenstein); AGARD-Bionics-Symposium, Brussels, Belgium, Sept. 1968
_______________
*) in German language
 
 
Contents of this page Links
Keynotes
Documented Invited Presentations
Awards etc.
Invited Presentations in International 
  Company Meetings
Invited Courses given
Other Invited Presentations
Contributions as a Panelist
Refereed Documented Presentations
Bio incl E.I.S. | detailed bio | short bio
Technical Presentations
Talks cumulative
Recent papers and talks
Papers and Books, categorized
Papers cumulative | books
Theses directed
Version with Alumni Prof links
Theses directed: with alumni links
Advisory Activities
Serving Conferences and Journals
Serving Professional Organizations

History of KARL | KARL users
History of E.I.S.
University of Kaiserslautern
Dept. of Computer Science
Tel: ++49/0 631 205 2606
Fax: ++49/0 631 205 2640
Email: hartenst@rhrk.uni-kl.de
http://www.fpl.uni-kl.de