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The E.I.S. Project and

other EDA Achievements

-> german version

TU KL

 KIT Institut für Technik der Informationsverarbeitung (ITIV) des Karlsruher Institut für Technologie (KIT)

 

E.I.S. (Entwurf Intergierter Schaltungen) (i. e.: Design of Integrated Circuits) has been the name of the German Mead & Conway style multi university VLSI design project including a multiproject chip organization. The E.I.S. project has been funded by the German Minister of Research and Technology (BMFT) from 1983 thru 1989. E.I.S. has been the forerunner of the EUROCHIP organisation funded later by the Commission of the European Union.

--> version in German language: also details how industry tried to block it!

 

The Early History of the Mead & Conway Revolution

  • In the 70ies Prof. Carver Mead from Caltech (California Institute of Technology) preaches, that in teaching on integrated circuits the technology should be separated from design: "The design (Design Sciences) must be its own discipline." Of course, technology professors did not like this idea: "This little bit of design we easily do on the fly with the left hand".

  • Winter quarter 1978: Lynn Conway as a guest professor at M.I.T. gives her famous VLSI course with design exercises. Second week of January in 1979 her students hold in their hands their designs as fabricated and packaged chips. During the Xmas / New Year break the student design had been checked  and merged to multi project chips at Xerox PARC (3333 Coyote Hill Drive, Palo Alto). A few years later this multi project chip organisation pionered by Lynn Conway has been taken over by the MOSIS Service at ISI (Information Sciences Institute in Marina del Rey, close to Los Angeles) of the University of Southern California (USC). The fabrication of the designs from Lynn Conway's M-I.T. students has been carried out on a Hewlett-Packard pilote fabrication line at Deer Creek Road, next street parallel to Coyote Hill Drive.

  • Apropos Xerox PARC: a fascinating literature is the book "Dealers of Lightning "

  • A well attended one week Mead-&-Conway course for professors took place in 1979 at Seattle ("professors back to school desk").

  • On the way home from a business trip to San Diego for DAC 1979 Prof. Hartenstein visits Prof. Carver Mead at Caltech, Pasadena, California.

  • Also in 1979 at a party in Berkeley Prof. Hartenstein gets introduced to Dr. Lynn Conway (head of the VLSI Lab at PARC). A few days later he holds in hands the prepublication copies of the first 4 chapters of the forthcoming book "C. Mead, L. Conway: Introduction to VLSI Systems", which appeared mid' 1980 from Addison Wesley 1980

  • During summer semester 1979 Prof. Hartenstein holds his first Mead-&-Conway style graduate couse (exercises included) "Einführung in den VLSI-Entwurf" at the University of Kaiserslautern - as the first "on the continent" (Europe and Asia). Only in UK, off shore from continent, a colleague did it 3 months earlier. Also see Lynn Conway's Reminiscences of the VLSI Revolution.

  • Industry did not like our Proposal

  • In February 1980 Prof. Hartenstein sends a VLSI multi university project proposal to  Regierungs-Direktor Dr. Hamacher at BMFT (German Ministry of Research and Technology). Dr. Woelcken talks about details of this conflict in his jubilee lecture at IMEC.

  • For March 19, 1980, from 9.00 a.m. til about noon Dr. Hamacher invites to a meeting within BMFT. Attendees have been: Dr. Klaus Berkling (GMD), Prof. Dr. Walter Engl (RWTH Aachen), Dr. Hamacher (BMFT), and Prof. Reiner Hartenstein (TU Kaiserslautern). Prof. Engl, a technologist having had worked for years as a consultant to Dr. Hamacher, meant: "Carver Mead is a charlatan". He mentioned, that, instead of going to Coyote Hill Drive he went to Deer Creek Road (where Lynn Conway`s chips have been fabricated) to find out "the real truth" - a technologist's point of view on design. Dr. Hamacher believed him. At the end of the meeting Dr. Berkling and Prof. Hartenstein felt having been thrown out first class.

  • At a NATO ASI (Advanced Study Institute) on Very Large Scale Integrated Circuits held July 7 - 18 in 1980 at Louvain-La-Neuve, Belgium, Dr. Lynn Conway had been scheduled with 4 talks. But because of political issues of the Reagan administration the Xerox headquarters did not allow Dr. Lynn Conway to attend. Two of Lynn Conways talks have been given by  Prof. Carlo Sequin (UC Berkeley) and the other two by Prof. Reiner Hartenstein (TU Kaiserslautern).

  • July 20 thru August 1 Prof. Paolo Antognetti (Univ. Genua) und Prof. Don Pederson (UC Berkeley) held another NATO ASI on VLSI Design Methods at Urbino, Italy, with about 80 attendees. Also exercises have been part of the schedule, where EDA software running on a VAX was used to input design problem examples. The terminals being unbelievably extremely slow was massively frustrating. In the basement of the building Prof. Hartenstein detected a punched card reader connected to the VAX. In using this museum-type equipment to create the punched card deck and its input to the VAX was by several orders of magnitude faster than by the VAX terminals. He held already the plot of his design in his hand while all other attendees had keyed in only a small fraction of their exercise code. At August 2 in 1980 the railway main station of Bologna has been blown up by terrorists - only a few minutes after the Gotthard Express had left the station with Prof. Hartenstein on board, who has been on the way home from Urbino.

  • Successful second Application for Funding

  • At the annual "Schlosstag" at Schloss Birlinghoven on October 1 in 1980 Prof. Norbert Szypersky quasi celebrated his debut as the new CEO of GMD. In front of the dinner buffet he had a lengthy talk with Prof. Hartenstein, meanwhile back home from UC Berkeley where he had been a visiting professor. The queue of other guests waiting for shake hands with the new CEO was growing longer and longer. VLSI became a matter of the boss and Dr. Woelcken, head of Prof. Szypersky's staff, was put into charge at very high priority.

  • September 27 thru 29 in 1982, the GMD Research Center at Schloß Birlinghoven, gave a course for scientists ("professors back to school desk") on VLSI design with Prof. Hartenstein as the only speaker.

  • Because of high demand this course has been split up into 2 courses. The second one has been held October 18 thru 20 in 1982, also at Schloß Birlinghoven. At a social event in the evening of the second day Dr. Woelcken (GMD) and Reiner Hartenstein have set up a pressure group from bunch of professors.

  • Toward the end of 1982 Prof. Seitzer (Univ. Erlangen-Nuremberg), Prof. Waldschmidt (Univ. Frankfurt) and Prof. Hartenstein met in a hotel close to the Autobahn cross Biebelried for coordination of the pressure group.

  • After elections in 1983 Helmut Kohl having promised "die große Wende" (the great turning point) became Bundeskanzler, and Dr. Heinz Riesenhuber became R&T minister, which turned out to be "die große Wende" for the pressure group mentioned above.

  • In 1983: Dr. Woelcken sends a proposal the successor of Dr. Hamacher, simultaneously with a letter by Prof. Hartenstein addressed to the minister in person. (Prof. Hartenstein had met Dr. Riesenhuber already in the 70ies.)

  • Toward the end of 1983 a grant of about 38 million Deutschmark has been approved for Prof. Hartenstein to run the multi university E.I.S. project for 3 years. See the E.I.S. landscape.

  • In 1987 the E.I.S. project has been extended by another 18 months with a second grant.

  • Introducing the M-&-C Revolution to the Continent

  • Around 1980 or slightly later in every Western European Country a collegue practiced lobbying for M-&-C at the national technology ministry. However, always the reply has been the same: "None of our neighbour countries is supporting this. Why should we fund it?". As soon as my application in Bonn was successful, all these colleagues again went to their technology ministers telling, that now a neighbour country is funding it. This has removed the Europe-wide M-&-C deadlock.

    International Technology Transfer

  • Around 1989 the EUROCHIP organization has been set up after extensive lobbying activities by Prof. Hartenstein and by Dr. Woelcken, as soon as he had left GMD to join the Commission of the European Union. Via knowledge transfer by the person Dr. Woelcken the E.I.S. Projekt became the incubator of the EUROCHIP ACTION still running to-day. In 2009 IMEC organized the anniversary symposium "20 years EUROCHIP-EUROPRACTICE", where als Dr. Woelcken gave an interesting talk: "EUROCHIP, the birth of a strategic action".

  • 1982 - 2004: Prof. Hartenstein gives a major series of colloquium talks and and other invited presentations, as well as courses, also 3-day and 5-day courses in different countries. 

  • 1982 - 2003: Prof. Hartenstein gives a major series of other invited presentations in different countries throughout Europe. 

  • 1982 - 2002: Prof. Hartenstein's contributions as a panelist in different countries throughout Europe. 

  • M-&-C-based consulting to Siemens AG, DLR (German Aerospace Center), PACT Corp.,

  • Hartenstein was Laureate guest of the E.I.S. Anniversary Workshop at Dresden, Germany, April 3 - 5, 2001.

 

E.I.S. Workshops:               

 
  5. E.I.S.-Workshop, Dresden, 8. - 9. April 1991
4. E.I.S.-Workshop, Bonn, 21. - 22. Februar 1989
E.I.S. CAD-VLSI summer school, Schmitten/Taunus, 1988
3. E.I.S.-Workshop, Bonn, 13.-14. Oktober 1987
2. E.I.S.-Workshop, Bonn, 4. - 5. März 1986
1. E.I.S.-Workshop, ?
2. pre-workshop course*, St. Augustin, 18. - 20. Okt. 1982
1. pre-workshop course*, St. Augustin, 27. - 29. Sep. 1982
    *) 3 or 5 day course fully presented by Reiner Hartenstein
12. E.I.S.-Workshop, ?
11. E.I.S.-Workshop, Erlangen, 31. März - 1. April 2003
10. E.I.S. Workshop, Dresden, 3. - 5. April 2001
9. E.I.S.-Workshop, Darmstadt, 22. - 24. Sept. 1999,
8. E.I.S.-Workshop, Hamburg, 8. - 9. April 1997
7. E.I.S.-Workshop, Chemnitz, 7. - 8. November 1995
6. E.I.S.-Workshop, Tübingen, 25. - 26. Nov. 1993
?. E.I.S.-Workshop, St. Augustin, 19. - 20. Nov. 1994
-
 
     
 

>34 invited courses given: most of them 3 days or even 5 days

>300 other invited presentations:

Microchips having been manufactured for the E.I.S. Project

 
     

E.I.S.-influenced later Projects by R. Hartenstein

M-&-C style Hardware Description Languages (HDLs)

  • M-&-C-influenced, Hartenstein's KARL language was the first VLSI design oriented HDL- not merely architecture-based as other HDLs at that time. During the 80ies is has been the world-wide leading design language. Why mainly only in the 80ies? Click here.

  • Based on its Domino-Notation KARL was the first HDL system including a VLSI-oriented graphic user interface ABL ("A Block diagram Language").
  • Hartenstein coined the term ⇒ "Structured Hardware Design" ⇐ in 1974 in a paper for a conference in Palo Alto. Lynn Conway means, this has inspired Carver Mead to create the term ⇒ "Structured VLSI Design". ⇐

  • KARL was in the 80ies with 93 licensee institutions the ⇒ worldwide leading hardware description language. ⇐ 29 KARL-based modules supported other EDA software implementers. Also see the quotation index and KARL-related literature.

  • KARL was the backbone of the worlds's first complete "VLSI design framework" (see Fig. 33), developed by the CVT-Project and its successor, the CVS-Project. both funded by the commission of the EU with 85 million € (at that time called "ECU").

  • KARL became the trailblazer of Term Rewriting (TRS) in EDA for Synthesis by a top-down approach, whereas all other TRS use in EDA is for verification, i. e. bottom-up. Already before 1980 this was demonstated by designing an integer multiplier from the math formula. TRS expert Prof. Mauricio Ayala-Rincon found out 25 years later that this method is world-wide ⇒ for EDA hardware design still the only TRS top-down approach ⇐.

  • After having spent more than 85 Million € (ECU) for funding the development of a KARL-based VLSI-EDA-Framework the officers of the EU commission decided in May 1989 in a meeting in Nice, France,, ⇒ to finish the funding of hardware description languages ⇐ with the argument: "since now there is standard: VHDL". However, this justification has been false, since VHDL was even not yet inplemented and a standardization proposal did not yet exist. This EU decision has been manipulated by the same DoD-supported and NATO contacts using aggressive VHDL lobby which a few years later also killed CHDL, at that time the only serious and well frequented international conference series in this area.

Mead-&-Conway Style early Achievements in Reconfigurable Computing

  • For the implementation of the MoM Xputer reconfigurable microprocessor the first FPGAs appearing on the market have been by far too small. For replacing these FPGAs a much more area-efficient "DPLA" was designed by Hartenstein's group and manufactured by the E.I.S. project multi project chip organization. One such DPLA replaced 256 FPGAs. Based on this DPLA the PISA Project for the vN to RC migration of a VLSI Design Rule Check Programm Hartensteins group achieved a ⇒ speed-up factor of 15.000 ⇐ by 2 decades ahead of the state of the art (see below for the graphics figure).

  • Hartenstein's reconfigurable computing perspectives caused a growing number of invitations to give keynote addresses. Also see http://hartenstein.de/PARC.htm.

  • Hartenstein was invited for consulting by PACT Corp., THALES, and DaimlerChrysler AG. The cooperation with DaimlerChrysler lasted many years and also created an "automotive FPGA" by Xilinx Corp.
        

  • guest, Opening Ceremony of the DFG Priority Research Program (SPP 1148) on Reconfigurable Computing Systems; DaimlerChrysler Conference Center at Untertürkheim, Germany, June 12 - 13, 2003 (DFG = German National Research Foundation).

  • Early Achievements in Datastream-based Computing (for  M-&-C-based applications)

  • The M-&-C style  trailblazing role in Datastream-based Computing by Hartenstein propargates the ⇒ "Anti-Machine" paradigm ⇐, also called Xputer. This is the counterpart of the von Neumann paradigm by using data counters instead of a program counter.

  • A very important first step toward data-stream-based computing was the      generalization of the systolic array, which Reiner Hartenstein invented and implemented together with his Ph.D. student Rainer Kress. (also click here)

  • The PISA project implemented a Design Rule Checker based on Lynn Conway's Lambda-grid-based design rules: see the picture from a paper. Running on Hartenstein's "MoM Xputer" hardware it obtained a speed-up by 4 orders of magnitude, already ⇒ 2 decades earlier ⇐ than all other studies demonstrating the benefit of using FPGA-based accelerators.

  • In 1996 Hartenstein's team was invited to give a tutorial for ARM, Ltd. at Cambridge.  

    The von Neumann syndrome requires a kind of
    partial reissue of the Mead & Conway revolution,

  • Now after 30 more years we again must reinvent computing scheince. - because of the von-Neumann-Syndrom the growth of the internet and of other ICT infrastructures will lead to uaffordably high electricity consumption at some time in the next decade: Computers are Facing a Seismic Shift. We need a new a new E.I.S. Project - namely a thoroughgoing improved and retargetted new edition - based on Kaiserslautern's Xputer paradigm: the counter-part of von Neumann by using data counters instead of a program counter.

  • Originally each abstraction level has been its own very special area and specialists from different levels had extreme problems in understanding each other. That's why the most important feature of ther Mead & Conway revolution has been the ⇒ "Tall Thin Man" ⇐:. Each abstraction level has been drastically cleared out, so that a single person can easily understand everything up and down throughout all levels [2]: the Tall Thin Man!

  • Meanwhile another secret of success of the Mead-&-Conway revolution is fading away: namely Moore's Law. This is coming along with the many-core-related pressure to program parallel processes. The traditional separation between hardware and software has become unusable. So far the Tall Thin Man has been qualified only up to the register transfer level. Now we urgently need a much taller ⇒ "Super Tall Thin Man" ⇐ which must be very much taller to reach also all higher abstraction levels til up to all kinds of multi-level memory structures and communication networks. See also a clip from Hartenstein's featured invited presentation in 2013 at Washington DC, USA: "The Tunnel Vision Syndrome". Hartenstein honored by the following ASAP Awards: this none and that one. Also see the list of his 50 keynotes )

  • Already a long time ago the paradigm shift over to ⇒ "heterogeneous systems" ⇐ has become inevitable, not only because of the economic pressure, to obtain a maximum number of compute operations per watt. Mike Flynn's taxonomy of computer systems, published in the 60ies (see the picture to the right) assumes, that computing is possible only with von Neumann processors. This Aristotelian World Model of computing must be replaced by a Copernican World Model supporting taxonomies not suffering from the tunnel visioh syndrome. This world model includes both: the von Neumann model and the Xputer paradigm. The Ph.D. dissertation of (meanwhile Professor) Diana Goehringer, supervised by Reiner Hartenstein extended this taxonomy from 4 to 16 ressource classes - distinguishing between reconfigurable (indicated by a little red prefix letter "r") and hardwired (see the picture above to the right).

  • However, meanwhile we must distinguish two different scenarios of Reconfigurable Computing. Recently Reiner Hartenstein supervised two Ph.D. dissertations about microprocessors with ⇒ reconfigurable instruction set ⇐: (Ralf König in 2012 and Timo Stripf in 2013). On the other side there are exclusively datastream-bases reconfigurable systems, which perform ⇒ computing without instruction streams ⇐ (for instance pipeline networks). This is an area where Hartenstein is recognized as "the father of Reconfigurable Computing" [Viktor Prasanna]. That's why Hartenstein extended Diana's taxonomy (s. picture at the right side) by adding another 4 classes for "no instruction stream". We see that the design space for different compute solutions has grown by an order of magnitude. To master this massive challenge Hartenstein calls for a A New World Model of Data Processing: a Copernican World Model of Comnputing..

  • What is the reason of the FPGA Marketing Paradox ? Despite of the by several orders of magnitude better performance and power efficiency the FPGA share of the semi market remained below 1.5 percent for more than 10 yeats. This is a globel economioc desaster, since FPGAs are urgently needed to prevent the future global energy supply collapse to be caused by the ⇒ von Neumann Syndrome ⇐. The FPGA marketing paradox is caused by a lack of programmers with the required new qualificaions and by the very bad productivity of the classical software engineer being a kind of disabled to serve the Copernican Computing World. Here the paper " ⇒ "Computing without Processors" ⇐ by Satnam Singh illustrates, how farreaching the methods of programming must be reinvented. Because of the questioned importance of instruction streams the term "Software Engineering" should be replaced by a new term yet to be coined. If you have an idea, please, e-mail it to Reiner Hartenstein.

Literature

[1]  Michael Hiltzik: Dealers of Lightning - Xerox PARC and the Dawn of the Computer Age; HarperCollins, New York, 1999

[2]  R. Hartenstein (eingeladener Vortrag): Reconfigurable Computing: Paradigmen-Wechsel erschüttern die Fundamente der Informatik; - Prof. Glesner's 60th Birthday Anniversary Colloquium; 29 Aug 2003, Darmstadt
   

            

 




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